SPI on STM32H743 idles half of the time during active data transmission

[Zhiyong Li]

Hi,

I am in the middle of migrating a project from STM32F767 to STM32H743. Both MCUs being compatible helped a lot.But there have been still a few road blocks, the last of which seems to be SPI. We use SPI3 to interface with a RA8875 based LCD. With DMA, we were able to get good results on F767, but so far not so much on H743. After connecting MOSI/MISO/CLK/CS lines to a logic analyzer, I noticed there both MOSI and CLK lines idle about the half of the time. Please see the screenshot below. During a supposedly active session of data transmission, either through DMA, or blocking write, there are several gaps. The measured during of those gaps are about either 5ms or 6ms.

My question is: when would a SPI instance go into idle state? waiting for TX data to be ready (related to the famous D-cache issue on H7)? 

Please advise. Thanks in advance.

ZL

 

 

[KDJEM.1]

Hello ​@Zhiyong Li ;

 

For SPI functionality, I recommend you to look at RM0433 section 50.4 SPI functional description.

Are you using HAL or LL drivers?

 

Thank you.

Kaouthar

[Andrew Neil]

Welcome to the forum

Please see How to write your question to maximize your chances to find a solution for best results.

 

Have you used your logic analyser to see what’s happening in each burst?

eg, does each burst represent exactly 1 DMA transaction?

 

Can you post a minimum but complete example which illustrates the issue?

[Zhiyong Li]

For anyone that paid attention to the issue or came here from a Google search, please understand this issue has nothing to do with MCU itself nor HAL from STM. The idling of SPI instance is scheduled by underpinning RTOS. There are some changes/differences in how SPI/DMA is managed by the software package (Mbed-OS) between F767 and H743. Sorry for wasting the time of anyone that was involved.