SPI DMA FIFO Error Issue (FEIFx)

[evan]

Posted on October 25, 2013 at 01:05

I'm having a terrible time diagnosing this error on an F407IG chip.  I am trying to TX/RX SPI via DMA.  Currently I am getting good transactions, according to the external logic analyzer, from lengths of 1 to hundreds of bytes.  However, each and every time instead of getting a transfer complete interrupt, I get a FIFO error instead.  The data makes it through just fine, every last bit of it, but the error occurs somewhere during the stream and seemingly prevents the transfer complete interrupt from firing.

According to the reference manual, this error disables the dma stream (EN bits in the DMAx_SxCR register), however the remainder of my data goes through, as if the module was running normally.  I have tried running the bus at low speeds (~200khz) up to about 10mhz with identical results. I have tried different SPI / DMA channel combinations as well as various combinations of FIFO settings (and disabling the FIFO altogether).  Nothing else is running on the chip, so theoretically there shouldn't be any memory bus contention or DMA channel contention.

Any thoughts or directions to take this would be incredibly helpful.

#spi-dma-fefi

[evan]

Posted on October 25, 2013 at 17:30

Issue is solved.  Info here if anyone else has the same problem.

The code was originally pulled from a working L1 build, the order of module enabling is different.  In L1 the SPI module is enabled before the DMA, while in the F4 the SPI enable should be the last step which initiates the transaction.

[Garnett.Robert]

Posted on April 22, 2016 at 11:16

Hi,

I had the same problem with an F7.  I am using the HAL drivers and found that they are enabling DMA before the SPI Enable, but I still had the problem with the FEIFx interrupt.  The HAL drivers always enable all Interupts so the FEFIx ends the transaction in the SPI IRQ handler.

I am not using the FIFO, so I ended up turning the FEIFx interrupt off.  It's not a very elegant solution.  I cannot see why the FEFIx error should be active when the FIFO is disabled.

Perhaps someone can explain this.