SPI Clock goes low when Cable Select does
Hello,
I am interfacing with a peripheral where code exists for Arduino, but using it as reference for STM32. The SPI mode is 3. The Arduino code works, so I am attempting to reproduce it's methods for communication. An issue I am seeing is that the SPI CLK signal is going low as soon as I lower CS. For instance, if you take a look at this snippet of code:
void pwm3901_write(uint8_t reg, uint8_t value) {
uint8_t buffer[2];
reg |=0x80u;
SPI1_CS_GPIO_Port->ODR %= SPI1_CS_Pin;
delay_us(50);
spi_transfer(®, 1);
spi_transfer(&value, 1);
delay_us(50);
SPI1_CS_GPIO_Port->ODR |= SPI1_CS_Pin;
delay_us(200);
}You can see that after setting SPI1_CS_Pin low there is a 50us delay. (Eventually I want to see if this can be removed, but first I need to mirror the Arduino code functionality to get this to work)
When I look at this with my logic analyzer, I am seeing this:
As soon as CS goes low, so does CLK. This doesn't make any sense to me because they are completely independent of each other. This causes an issue with the data. I am expecting the first byte to be 0xBA (10111010), but instead it is 0x5D(01011101)
The equivalent output on the Arduino looks like this:
I just set CS to low, without an SPI transaction the same thing occurs:
However, this seems to begin acting normally after the first "write":
I thew a 10K pull up resistor in there, and it's still being drawn down.
