spi clock error in STM32L431

[cai.bai]

Posted on March 10, 2017 at 09:32

hi,I want use SPI1 as master and SPI1 reg configure as that

    SPI1->CR2 =

0x1704

;     SPI1->CR1 =

0x15C

;

read code is

    GPIOA->BSRR |=

1

<<

20

;

//set NSS low

   

for

(i =

0

;i < command_size;i++)

{

       

while

(

0

== (SPI1->SR & SPI_SR_TXE));         SPI1->DR = out_buf

[

i

]

&

0xFF

;        

while

(

0

== (SPI1->SR & SPI_SR_RXNE));         in_buf

[

i

]

= SPI1->DR &

0xFF

;    

}

    GPIOA->BSRR |=

1

<<

4

;

//set NSS high

i use logic analyzer capture the logic as

it saw that clock also driver after NSS set high.

can anyone help me

#stm32l431-spi

[S.Ma]

Posted on March 10, 2017 at 09:56

Release NSS only when SPI BUSY bit is cleared.

[cai.bai]

Posted on March 10, 2017 at 10:00

thank you for reply, my problem is that when i send 3 bytes but it have 48 clocks

[S.Ma]

Posted on March 10, 2017 at 10:27

https://community.st.com/0D50X00009XkfrtSAB

  Should give the solution.