Question
Sources which generate SAI_CK_A on STM32F7?
Posted on September 12, 2016 at 04:31
The problem is that I have an *external* 24.576 MHz MCLK. In master mode, how do I get that from outside the chip onto the SAI_CK_A or SAI_CK_B clock?
I was going through section 36.3.1 ''SAI block diagram'' and figuring out how to wire everything up.If the STM32F7 is a slave, things mostly make sense: SCK maps to BCLK, FS maps to FCLK or LRCLK, SD maps to data. Presumably, MCLK is ignored--that's a little scary but I guess it could work given that the audio block has FIFOs.If the STM32F7 is a master *AND* generates the clock, then things are perfectly straightforward: MCLK is generated and maps to MCLK, SCK maps to BCLK, FS maps to FCLK or LRCLK, SD maps to data. The reference manual mumbles in section 36.3.7:The clock source for the clock generator comes from the product clock controller.
Okaaaay. I don't see anything in the manual about an SAI product clock controller. Nothing is listed which directly drives SAI_CK_x in Figure 429.Any help would be appreciated.Thanks. #sai-mclk-m7-stm32f7