SMT32F7; FMC with SDRAM & NAND Problem.

[David George]

Posted on February 16, 2018 at 15:53

I have a problem with an STM32F767 on a custom board with SDRAM and NAND SLC memory connected to the FMC.

The NAND is 8 bit, the SDRAM is 32bit, so only the [D0:D7] signals are shared between the SDRAM and the NAND.

• When both the SDRAM and the NAND are configured & working any NAND data read is corrupted randomly.
• When just the NAND is configured the NAND data read is correct.
• The SDRAM always works fine with or without the NAND.

The LTDC uses the SDRAM to hold its frame buffer - it uses the DMA2D to read the current frame from SDRAM at regular intervals.

The SDRAM initialises and tests ok, I can see good display data on my display (no bad pixels or image corruption).

However when I test the NAND (Erase a block, read Pages from the Block) I get random read errors that don't reproduce the next time the Page is read (1 Page = 2048 bytes).

If I then disable the LTDC '__HAL_LTDC_DISABLE(&hltdc);' the NAND works perfectly with no read errors.

So I conclude the DMA2D reading the SDRAM is causing interference when reading the NAND?

Is there a way of locking the FMC while reading from the NAND, or if the FMC memory reads get interlaced should this be ok?

Example.

DMA2D is reading a LTDC frame from the SDRAM (431KB of data) using the FMC.

A NAND Read starts using the FMC - does this interrupt the DMA2D read process? or do they get mixed up?

Any help or pointers would be appreciated.

#mpu.

[David George]

Posted on February 21, 2018 at 09:51

The solution turned out to be with the Cortex M7's

#

My adding MPU Regions for;

• the FMC Bank 3 (NAND Flash) that is NOT Bufferable, Shareable or Cacheable
• the FMC Bank 1 (SDRAM) that is NOT Bufferable, Shareable or Cacheable

allowed the NAND to be Read correctly even when the SDRAM was being accessed.

While looking at the MPU its best to add regions for all your system memory, there is a good App-Note from ST on this

http://www.st.com/content/ccc/resource/technical/document/application_note/group0/bc/2d/f7/bd/fb/3f/48/47/DM00272912/files/DM00272912.pdf/jcr:content/translations/en.DM00272912.pdf

/* Region 2.

     * Configure MPU region attributes for the NAND Flash address space.

     * FMC Bank 3 = NAND, 192kB space used.

     * 0x8000_0000 Data

     * 0x8001_0000 Cmd

     * 0x8002_0000 Addr

     * Memory Type = DEVICE

     */

    MPU_InitStruct.Number = MPU_REGION_NUMBER2;

    MPU_InitStruct.Enable = MPU_REGION_ENABLE;

    MPU_InitStruct.BaseAddress = 0x80000000;

    MPU_InitStruct.Size = MPU_REGION_SIZE_1MB;

    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;

    MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

    MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;

    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;

    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL2;       // = DEVICE

    MPU_InitStruct.SubRegionDisable = 0x00;

    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;

    HAL_MPU_ConfigRegion(&MPU_InitStruct);

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