Should SSM be 0 or 1 when using SSOE=1?

[CHead]

According to reference manual section 49.4.7 (Slave select (SS) pin management), “Hardware SS management (SSM = 0): in this case, there are two possible configurations … SS output enable (SSOE = 1)�?.

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However, according to reference manual section 49.11.4 (SPI_CFG2 register details), there is a note under the description of the SSM bit that says, “SS signal input has to be managed by software (SSM=1, SSI=1) when SS output mode is enabled (SSOE=1) at master mode.�?

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So when SSOE=1 and hardware-controlled SS is desired, should SSM be 0 or 1? According to 49.4.7, it should be 0; according to 49.11.4, it should be 1. Experimentation suggests that it doesn’t matter. It would be nice for ST to say which configuration is guaranteed to work properly.

[S.Ma]

If you want HW control of NSS, make sure the signal reaches a GPIO where the alternate function is properly programmed. For SPI master mode, HW function may be of value in TI pulse mode mostly.