Sharable D1 SRAMs in the more recent H7 chips

[HWidj.2]

As per RM0468, STM32H72x and STM32H73x chips have 192 KB of SRAM in the D1 domain that is 'sharable' between ITCM and AXI SRAM, ie. it can be allocated as ITCM or AXI SRAM with 64KB granularity,

It is known that SRAMs in D1 (or any other domain for that matter) generally has slower access time than the TCM, now, if that sharable 192 KB chunk of memory is configured as ITCM will it be as fast as the ITCM?

[HWidj.2]

Right after posting the question I stumbled open AN4891 which has a very detailed block diagram (page 10). Turns out the shareable D1 SRAM is dual ported, with one dedicated bus directly connected to the TCM bus, so seems like the answer is yes it will be as fast as ITCM when configured as one.