Setting up a UART caused device reset

[Jemegen]

I am trying to build a uart implementation from scratch to learn the Stm32, but such a code implementation seems to cause my Stm32F030 to go into Reset_Handler state.

What might be wrong with my code? Thanks in advance!

 

 

void uar2_rx_tx_init(void)
{
 USART2->CR1 = (USART_CR1_TE | USART_CR1_UE | USART_CR1_RE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE);
 RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
 RCC-> APB1ENR |= UART2EN;
 GPIOA->MODER ^= ~(1U<<6);
 GPIOA->MODER |= (1U<<7);


GPIOA->AFR[0] |= (1U<<12);
 GPIOA->AFR[0] &= ~(1U<<13);
 GPIOA->AFR[0] &= ~(1U<<14);
 GPIOA->AFR[0] &= ~(1U<<15);
 //USART2->CR3 |= RCC_CFGR3_USART2SW_SYSCLK;
 uart_set_baudrate(USART2, APB_FREQ, UART_BAUDRATE);


}

uint16_t uart2_read(void) {
 while(!(USART2->ISR & USART_CR1_RXNEIE))
 {

 }
 return USART2->RDR;
}
static void uart_set_baudrate( USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaduRate)
{
 USARTx->BRR = compute_set_baudrate(PeriphClk, BaduRate);
 //USARTx->BRR = 0x45;
}

static uint32_t compute_set_baudrate(uint32_t PeriphClk, uint32_t BaudRate)
{
 return ((PeriphClk + (BaudRate/2U)) / BaudRate) ;
}​

 

 

[waclawek.jan]

> such a code implementation seems to cause my Stm32F030 to go into Reset_Handler state.

At which line?

JW

[Jemegen]

I tried to attach my debugger and I can tell this code is causing reset:

 

 GPIOA->MODER ^= ~(1U<<6);

 

To be exact, it's command at 0x08000368

[Tesla DeLorean]

You'd want to enable the USART2 clock, before writing register.

Check external connectivity to see if that triggers a short or reset.

Doing multiple RMW is also not very efficient. Fold so there's a single load/store instead of multiple.

[waclawek.jan]

^ means XOR. You probably want &, i.e. AND.

JW

[Jemegen]

It works! Thanks for your help!