SDRAM configuration for 216MHz sysclk.

[VVasi.1]

Hello, with a STM32F7508-DK board, all examples using SDRAM have the sysclk to 200MHz, therefore the FMC clock to 100MHz.

I am trying to enable sysclk = 216MHz, and FMC = 108MHz, so I followed the SDRAM user manual, and configured the following settings, which seem correct to me:

#define REFRESH_COUNT                   ((uint32_t)0x0684)  /* SDRAM refresh counter (108Mhz SD clock) */

 /* Timing configuration for 108Mhz as SDRAM clock frequency (System clock is up to 216Mhz) */

 Timing.LoadToActiveDelay   = 2;

 Timing.ExitSelfRefreshDelay = 8;

 Timing.SelfRefreshTime     = 5;

 Timing.RowCycleDelay       = 8;

 Timing.WriteRecoveryTime   = 3;

 Timing.RPDelay             = 3;

 Timing.RCDDelay            = 3;

However, even with these timings for the SDRAM (of course I set the PLL for 216MHz sysclk), I have random faults when accessing the SDRAM.

So my question is:

• does STM has a working example with SDRAM configuration when FMC = 108MHz?
• does anyone else have this?

HW reference:

• MT48LC4M32B2B5-6A: SDRAM external memory mounted on STM32F7508-Discovery board.

[berendi]

Look for SDRAM waveforms and timings in the datasheet.

[VVasi.1]

Well, that is the point, I did all that and below the computation I did:

• To support frequencies over 100MHz, I switched to CAS Latency 3 for the SDRAM, also increased the SDRAM GPIOs speed to max (OSPEED HIGH)
• Then, I analyzed both IS42S32400F-6BL (ISSI) and MT48LC4M32B2B5-6A(MICRON) datasheets, as the STM32F7508-DISCO board seem to have either one. Based on the datasheets, I set:
  • #define REFRESH_COUNT                   ((uint32_t)0x0683) => 15.625 ns (64ms refresh per 4096 rows) * 108MHz - 20
  • Timing.LoadToActiveDelay   = 2; => tMRD = 2 clk cycles (Micron) or 12ns (ISSI)
  •  Timing.ExitSelfRefreshDelay = 8; => tXSR = 67ns (Micron) or 70ns (ISSI)
  •  Timing.SelfRefreshTime     = 5; => tRAS = 42ns (Micron and ISSI)
  •  Timing.RowCycleDelay       = 7; => tRC = 60ns (Micron and ISSI)
  •  Timing.WriteRecoveryTime   = 2; => tWR/tDPL = 1 clk + 7ns (Micron) and 2 clk (ISSI)
  •  Timing.RPDelay             = 2; => tRP = 18ns (Micron and ISSI)
  •  Timing.RCDDelay            = 2; => tRCD = 18ns (Micron and ISSI)

Still, I have a RAM test which is passing but I get random faults with incomprehensible CPU registers content when accessing the SDRAM, so clearly I am missing something.

My point is that if the board supports this as a max frequency, why doesn't STM provide a working configuration?

[berendi]

[VVasi.1]

Many thanks, I missed that. We can consider this topic closed