Scatter file issue - does RESET have to be located at the base flash address?

[BPric.557]

I'm somewhat new to scatter files and I'm trying to understand them better by doing some tests on a ST32F765 project (with 2mb flash at 0x0800 0000 - 0x081F FFFF).

This scatter file works OK:

LR_IROM2 0x08100000 0x00100000 { ; load region size_region (Sector 8 - Sector 11, single bank)
 ER_IROM2 0x08100000 0x00100000 { ; load address = execution address
	AppFileInfo.o (+RO) ;
 }
}
 
LR_IROM1 0x08000000 0x00100000 { ; load region size_region (Sector 0 - Sector 7, single bank)
 ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
 *.o (RESET, +First)
 *(InRoot$$Sections)
 .ANY (+RO)
 .ANY (+XO)
 }
 RW_IRAM2 0x20000000 0x00020000 { ; RW data
 .ANY (+RW +ZI)
 }
}

but this scatter file does not work:

LR_IROM2 0x08000000 0x00100000 { ; load region size_region (Sector 0 - Sector 7, single bank)
 ER_IROM2 0x08000000 0x00100000 { ; load address = execution address
	AppFileInfo.o (+RO) ;
 }
}
 
LR_IROM1 0x08100000 0x00100000 { ; load region size_region (Sector 8 - Sector 11, single bank)
 ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
 *.o (RESET, +First)
 *(InRoot$$Sections)
 .ANY (+RO)
 .ANY (+XO)
 }
 RW_IRAM2 0x20000000 0x00020000 { ; RW data
 .ANY (+RW +ZI)
 }
}

When I try the second scatter file, everything compiles/links ok and looks like I'd expect in the .MAP file, but my debugger has warnings about the T-bit of XPSR (a Cortex core register?) being 0 and won't let me reset/run.

If I simplify things further by eliminating the LR_IROM2 block in both scatter files above, I get the same result. It's OK to have the things starting at 0x0800 0000 but not at 0x0810 0000 for some reason...

It seems like something wants/needs the RESET vector to be pointed at 0x0800 0000? Can anyone help me understand rules for this - or additional settings/configuration to adjust?

[Vangelis Fortounas]

Hello

When core starts after Power On, execution starts from Reset Vector of Vector Table.

Vector table expected to be in position 0x00000000 (the reset value of SCB->VTOR) Starting Value is the initial Stack Pointer value

The address 0x00000000 of execution is placed at flash address 0x08000000 . (exceptions of this rule are specific for MCUs with advanced capabilities)

Vector Table can be relocated . Alignment rules exists.

Paragraph 2.5 from RM0410 explains also BOOT modes of device.

[BPric.557]

Thanks, that is super helpful! I see that the BOOT_ADD0 (in FLASH Option Bytes) appears to be set for the ST default value of 0xFF7F 0080 (ITCM-FLASH base address). That should cause a boot address of 0x0020 0000 ("Boot from Flash on ITCM interface") according to the register description (p101 of RM0410).

That raises two follow up questions:

1. Why does the 0x0020 0000 "Boot from Flash on ITCM interface" selection in BOOT_ADD0 seem to cause things to start execution at 0x0800 0000?
2. Where in the project configuration / source files can I change the flash option bytes to boot to a different address?

Is it generally a bad idea to reserve a section of flash (that includes the base address) for other purposes?

Thanks again!

[Tesla DeLorean]

>>Is it generally a bad idea to reserve a section of flash (that includes the base address) for other purposes?

It is generally more important to understand the MCU's expectations first.

The vector table needs to be available at boot, the vectors can point wherever you want. Typically it needs to be on a 512-byte boundary, ultimately depends on the size of the table, and the next power of two.

Memory can exist at multiple addresses, it can be shadowed, dual ported, or have cached / uncached views.

If you need the early smaller flash sectors for configuration or EEPROM emulation, make a hole, and put the vector table or loader up-front.