SB bit of DMA2D_OPFCCR register missing on STM32H7?
Dear Sir/Madam,
It seems that DMA2D_OPFCCR register SB bit described in the reference manual of the the STM32H7 (RM0433, page 721) is not implemented. Code generated by CubeMX is missing the definition completely, an attempt to set the bit directly from code has no effect the bit remains 0:
hdma2d.Instance->OPFCCR |= (1 << 8);
Also tried:
hdma2d.Instance->OPFCCR |= 0xffffffff;
Resulted in 0x300007
It seems that only RBS, AI, CM are implemented...
What could be causing this?
Is this a mistake in the reference manual?
Has the byte swap function of the output FIFO been omitted?
Background:
We have a display connected to an SPI peripheral, DMA is used to send pixel data from a framebuffer to that display.
The display expects RGB565 data in big endian format, like this:
byte0: R0[4:0] G0[5:3]
byte1: G0[2:0] B0[4:0]
byte2: R1[4:0] G1[5:3]
byte3: G1[2:0] B1[4:0]
etc.
This is fine for static artwork, which could be formatted this way. However we are planning to use DMA2D to render texts and alpha blend images. Looking at the RGB565 definition of the DMA2D (RM0433, page 697)
byte0: G0[2:0] B0[4:0]
byte1: R0[4:0] G0[5:3]
byte2: G1[2:0] B1[4:0]
byte3: R1[4:0] G1[5:3]
RGB565 little endian (right?). It seems that the even and odd bytes need to be swapped before they can be sent to the dispay. The SB bit of the OPFCCR register promises to do just that....
Does anybody have a fix for this issue?
Thanks in advance!
Best regards,
Martin Meijerman
