Reset timer output compare output with timer in one pulse mode

[JBerry]

I am using an STM32H742 MCU and have a timer with an output connected to the output compare function. The timer is triggered from another timer and set to One Pulse Mode. Basically I want the output to go high and stay high once the compare value is hit after being triggered by the other counter. That all seems to be working just fine.

Now, I want to be able to "reset" the timer so that the output goes back low and the timer can be triggered again. It is unclear to me what exactly I need to do to accomplish this. I can force the output value to be low by setting it to forced inactive mode, but it is not clear if once I switch it back to active on match if it will immediately go high or wait to be triggered again.

[waclawek.jan]

> it is not clear if once I switch it back to active on match if it will immediately go high or wait to be triggered again

Trigger just starts the counter (CNT). The "match" in output compare happens when the counter's value reaches the CCRx value.

JW

[JBerry]

Sorry, by "wait to be triggered again" I meant wait for CNT to reach CCRx again. That is, does OCxREF keep state behind the output mux? Or does forcing the output compare output to inactive clear OCxREF as well?

[waclawek.jan]

I don't understand. What do you mean by "output mux"?

OCxRef is the signal which is result of the Compare module, it is basically a latch controlled by the combination of Mode set in CCMRx.OCxM and the result of the CNT-to-CCRx comparator. Basically it's a latch. If you set OCxM to Force Low, OCxRef is set to low. If you then change OCxM to High/Low on Match, OCxRef will not change until a compare match occurs.

JW

[JBerry]

Okay, thanks, that answers my question. This is the diagram shown in the reference manual:

What I called the "output mux" is labeled "Output selector" here. Or that plus the rest of the chain.

[waclawek.jan]

I see.

That "selector" basically performs the AND/OR with a neighbouring channel's output in the Asymmetric and Combined modes.

The latching happens in "Output mode controller".

This is an evolutionary thing. Compare the same diagram in older STM32's RMs, e.g. RM0008 (that's for 'F1, the oldest).

JW