Solved
reset all MAC subsystem internal registers and logic - fail?
DMABR->SR should be auto-cleared when set 1.
I haven't modified code - auto generated by hal.
It always timeouts - any ideas why? I tried to extend timeout time - bit 0 is always 1.
Here is code from HAL:
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
{
heth->State= HAL_ETH_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
not available, please check your external PHY or the IO configuration */
return HAL_TIMEOUT;
}
}Bit 0 SR: Software reset When this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.
