Relocating Vector Table to AXISRAM in STM32H743

[Ahmed Elzoughby]

Posted on June 24, 2018 at 13:03

Hi,

I am using the Nucleo-H743ZI development board and trying to make an Interrupt driver for it. The driver has to support changing the vector table contents at runtime. So I made a copy of the vector table in the AXI SRAM at its first address (0x24000000)

typedef void(*voidPFn_t)(void);

static volatile voidPFn_t newVectorTable[_VECTOR_TABLE_SIZE] __attribute__ ((section('.sram_d1')));

void interruptInit() {

    volatile voidPFn_t* origVectorTable = (voidPFn_t*) SCB->VTOR;

    // copy the content of the original vector table into the new vector table

    for(uint32_t i = 0; i < _VECTOR_TABLE_SIZE; i++)

        newVectorTable[i] = origVectorTable[i];

    // install the new interrupt vector table

    SCB->VTOR = ((uint32_t) &newVectorTable);

}

I succeeded to copy the content of the original vector table and I could see that through the memory window of my IDE. Also I set the VTOR register to 0x24000000 and modified my new vector table correctly.

But the problem is when I fire an interrupt in my test example the cpu goes to execute the interrupt handler of the original vector table not my new vector table. I don't know why that happens.

#interrupt #stm32h743 #nucleo-h743zi #stm32h7 #vector-table #axi-sram

[Tesla DeLorean]

Posted on June 24, 2018 at 17:30

Suggest using the ITCM RAM at 0x00000000

[Ahmed Elzoughby]

Posted on June 24, 2018 at 21:49

Tried that, but nothing new. the same problem occurred.

[Tesla DeLorean]

Posted on June 24, 2018 at 23:04

I've tried relocating the vector table on an STM32H743I-EVAL, reasonably standard configuration, with caching enabled.

I can copy the vectors to ITCM RAM, and change the SysTick_Handler routine to point to another one, which outputs periodically so I can see it is using that one, and not the standard one.

void SysTick_Handler_New(void)

{

    static int i = 0;

    

    if (i == 0) putchar('*');

    i = (i + 1) % 1000;

    

  HAL_IncTick();

}

...

♯ define VECSYSTICK 15

...

newVectorTable[VECSYSTICK] = &SysTick_Handler_New; // SysTick Handler

I can see it transition to the newly pointed too code.

If I use AXI SRAM it vectors off some illegal address

[Abdelhamid GHITH]

Posted on June 27, 2018 at 14:17

Hi!

I think you are facing a cache coherency issue (

https://www.st.com/content/ccc/resource/technical/document/application_note/group0/08/dd/25/9c/4d/83/43/12/DM00272913/files/DM00272913.pdf/jcr:content/translations/en.DM00272913.pdf

for some details about cache & cache coherency).

newVectorTable[VECSYSTICK] = &SysTick_Handler_New; // SysTick Handler

/* perform a cache maintenance : can be optimized by using SCB_CleanDCache_by_Addr  */

SCB_CleanDCache();

SCB_InvalidateICache();

Br,

Abdel

[Tesla DeLorean]

Posted on June 27, 2018 at 17:20

Had tried SCB_InvalidateDCache_by_Addr(), working today. Evidence suggests no write-through/invalidation occurs on the I-Cache normally, ggrr!

[Tesla DeLorean]

Posted on June 29, 2018 at 03:18

Ok, so having cycled the power on the STM32H743I-EVAL, changing the RAM at 0x24000000, resulted in the failure of SCB_InvalidateDCache_by_Addr() to achieve the goal, and the SysTick vectors off to some to some random junk.

SCB_InvalidateDCache_by_Addr((uint32_t*)newVectorTable, VECSIZE);

[Vitaliy Kostyrev]

Posted on June 29, 2018 at 04:10

extern

uint32_t __Vectors[];

/* vector table ROM */

#define VECTORTABLE_SIZE (256)

/* size Cortex-M7 vector table */

#define VECTORTABLE_ALIGNMENT (0x100ul) 

#define ADDRESS_SRAM *(uint32_t*)0x2400000

#define NEXT_ADDRESS_SRAM(A) (ADDRESS_SRAM+(A))

/* next power of 2 = 256 */

/* new vector table in RAM */

uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));

/*----------------------------------------------------------------------------

SysTick_Handler

*----------------------------------------------------------------------------*/

volatile

uint32_t msTicks = 0;

/* counts 1ms timeTicks */

void

SysTick_Handler(

void

) {

msTicks++;

/* increment counter */

}

/*----------------------------------------------------------------------------

SysTick_Handler (RAM)

*----------------------------------------------------------------------------*/

volatile

uint32_t msTicks_RAM = 0;

/* counts 1ms timeTicks */

void

SysTick_Handler_RAM(

void

) {

msTicks_RAM++;

/* increment counter */

}

/*----------------------------------------------------------------------------

MAIN function

*----------------------------------------------------------------------------*/

int

main (

void

) {

uint32_t i;

for

(i = 0; i < VECTORTABLE_SIZE; i++) {

NEXT_ADDRESS_SRAM(i)

= __Vectors[i];

/* copy vector table to RAM */

}

/* replace SysTick Handler */

NEXT_ADDRESS_SRAM

[

http://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7

+ 16] = (uint32_t)SysTick_Handler_RAM;

/* relocate vector table */

http://www.keil.com/pack/doc/CMSIS/Core/html/group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013

();

SCB->VTOR = (uint32_t)&vectorTable_RAM;

http://www.keil.com/pack/doc/CMSIS/Core/html/group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199

();

http://www.keil.com/pack/doc/CMSIS/Core/html/group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27

();

http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f

();

/* Get Core Clock Frequency */

http://www.keil.com/pack/doc/CMSIS/Core/html/group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427

(

http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6

/ 1000ul);

/* Setup SysTick Timer for 1 msec */

while

(1);

}

[Vitaliy Kostyrev]

Posted on June 29, 2018 at 04:12

SCB-> VTOR = (uint32_t) &

ADDRESS_SRAM

;