Really poor clock quality on the Nucleo-H753ZI board

[John.Sager]

I'm trying to use a Nucleo-H753ZI board for an audio (SPDIF) project and, compared with the Nucleo-F746 board I was using, the clock quality is abysmal - off frequency and with loads of phase noise. It appears to be derived from the HSI on the ST-LINK device (F723) rather than the 25MHz crystal oscillator (why 25MHz, why not 8MHz?). Has anyone else had issues with this? I've raised a support case with ST (case no 145713) but I'm not expecting a ST-LINK software fix anytime soon, even if it is possible.

[TDK]

The clock that the ST-Link provides the chip is configurable on these boards. During ST-Link upgrade, you can select from HSI-based 8 MHz or HSE/3 (8.33 MHz).

[John.Sager]

Ah, right. I didn't notice that when I first plugged the board in and it wanted to upgrade ST-LINK. I'll have to think about 8.33MHz. It doesn't really play too well with multiples of 48kHz for audio, but I may find some appropriate PLL settings. Thanks for the tip anyway.

[Nikita91]

How to get 480 MHz from 8.3333 HSE ?

CubeMX failed to find a solution...

[Tesla DeLorean]

Probably runs at 499.99 MHz just fine..

Could probably hit 479.16 or 483.33, I'd have to code a fitter to be sure.

There's an HSI48 for USB

Modifying HSE_VALUE would help get bauds within specs.

[John.Sager]

You can't, not exactly. However I put in 8.33333333 MHz to MX, which is well into 1ppm territory and much better than the actual crystal oscillator spec. With DIVN1 at 115 and the fractional-N set to 1638 on the main PLL I can get a system frequency of 479.999777 MHz which is not bad. The drawback of fractional-N in some critical applications using the ADCs is that the process introduces some clock jitter as the N1 divider is at 115 some of the time and 116 the rest of the time. For my app with SPDIF it's not a problem as the jitter is far less than with the HSI clock and I'll have an easier time building a tracking loop to set the output packet rate to follow the input rate.

[Nikita91]

Thank you! I did not know FRACN1.

What is the advantage of using a 25 MHz quartz instead of 8, 16, or 24, which make it easier to obtain exact frequencies?

[John.Sager]

They are probably cheaper by a few cents, as millions are made for Ethernet clocks. ST did up the speed of USB for ST-LINK3 but I can't really see why that would make a difference from using an 8MHz HSE.

[LCE]

What about placing an extra quartz or oscillator on the Nucleo board, or doesn't this one have an extra footprint?

Anyway, I found that SPDIF is one of the best ways to check clock quality, if you can connect to an SPDIF receiver with analyzer / FFT function.

It was really amazing to see the difference between HSI and HSE on 2 Nucleo boards (G4, F7) (SPDIF signal: 24 bit / 192 kHz with a math.h calculated sine wave).

I was surprised about both:

• HSI - completely crappy and unusable, signal quality was reduced to 10 bit (can't remember exactly, but felt like that)
• HSE with 8MHz from the ST-Link, signal was at least as good as my RX side with a CS8422

It was the first time I used an STM32 for audio, and especially the PLL / "clock creation" quality was surprisingly good.

[John.Sager]

I've tested with 8.333MHz (25/3), and it's probably acceptable for SPDIF, though there is a bit of jitter from the fractional-N PLL I used to get close to 480MHz. However I bought some Kyocera KC3225K 8MHz devices and a friend has mounted one up on a little PCB with some pins, so I'll use that as an external clock.

[Nikita91]

You can place an extra quartz on the X3 footprint.

You have to set 2 capacitor and move some solder drops.

Refer to the avalable board schematics.

[waclawek.jan]

> What is the advantage of using a 25 MHz quartz instead of 8, 16, or 24, which make it easier to obtain exact frequencies?

They could not use the 8MHz crystal used in older STLinks, given the 'F723's USB HS_PHY PLL limitations, see RM0431 USBPHYC_PLL1.PLL1SEL.

They could've used 16 or 24MHz, though. They really did not think about usability - probably some young ambitious but unexperienced crew. The ample usage of the unobtainium ARM-pushed connectors instead of the bog standard 100-mil headers, is telling, too.

JW