RCC_CFGR_MCOXPRE doesn't corrosponde to the manual

[uli stone]

Posted on August 17, 2017 at 21:15

Hi,

has anyone checked in the stm32f4xx.h Lib the RCC_CFGR_MCOxPRE Register?

The values mentioned in the RM0090 manual don't fit the stm32f4xx.h

stm32f4xx.h:

&sharpdefine  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)

&sharpdefine  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)

&sharpdefine  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)

&sharpdefine  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)

&sharpdefine  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)

&sharpdefine  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)

&sharpdefine  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)

&sharpdefine  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)

Manual RM0090:

Bits 27:29 MCO2PRE: MCO2 prescaler

Set and cleared by software to configure the prescaler of the MCO2. Modification of this

prescaler may generate glitches on MCO2. It is highly recommended to change this

prescaler only after reset before enabling the external oscillators and the PLLs.

0xx: no division

100: division by 2

101: division by 3

110: division by 4

111: division by 5

Bits 24:26 MCO1PRE: MCO1 prescaler

Set and cleared by software to configure the prescaler of the MCO1. Modification of this

prescaler may generate glitches on MCO1. It is highly recommended to change this

prescaler only after reset before enabling the external oscillators and the PLL.

0xx: no division

100: division by 2

101: division by 3

110: division by 4

111: division by 5

Bit 23 I2SSRC: I2S clock selection

Can anyone verify this, or I'm just mixing something up?

Thanks

#stm32f4xx.h #stm32f4 #register #error

[Tesla DeLorean]

Posted on August 17, 2017 at 21:45

>> I'm just mixing something up?

The define describe bit positions, not numeric values from the table

ie MCO2 setting of 5 would be

RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 // 111 = DIV5

[Tesla DeLorean]

Posted on August 17, 2017 at 21:46

 ,

 ,

I might do this

♯ define RCC_CFGR_MCO2PRE_DIV5 (RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

[uli stone]

Posted on August 17, 2017 at 23:10

Thanks Clive,

ya superb!