Questions about SPI6 and BDMA

[pass3master]

We are trying to transmit data using SPI6 and BDMA.
When we perform the following process, we are able to transmit 1 byte + 1 bit of data, but after that, MISO outputs High no matter what the value of the transmitted data is. What is wrong with this?

 

 

 

#define __ATTR_RAM_D3 __attribute__ ((section(".RAM_D3"))) __attribute__ ((aligned (4)))
uint8_t g_spitxbuf[4] __ATTR_RAM_D3; // DCDC基板温度センサ模擬_送信バッファ

 uint8_t rx_buf[2] = {0};
 uint8_t tx_buf[2] = {0};

 /* SPI3_CS High出力 */
 HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_SET);

 /* SPI3_CLKを有効 */
 __HAL_SPI_ENABLE(&hspi5);

 /* SPI3_CS Low出力 */
 HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_RESET);

 g_spitxbuf[0] = 0xA5;
 g_spitxbuf[1] = 0x00;
 g_result = HAL_SPI_TransmitReceive_DMA(&hspi6, g_spitxbuf, rx_buf, 2);
 g_result = HAL_SPI_TransmitReceive(&hspi5, tx_buf, rx_buf, 2, 1000);

 /* SPI3_CS High出力 */
 HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_SET);

 

 

[Sarra.S]

Hello @pass3master, 

That's normal, because BDMA does not have access to the resources located outside D3

g_spitxbuf is placed in the D3 domain, which is accessible with BDMA, however, the other buffers,rx_buf and tx_buf, should also be placed in D3 domain. 

The D3 domain includes AHB SRAM4, which is is accessible by most of the system masters through the D3 domain AHB matrix. So, you should remap your buffers to SRAM4. 

You can check BDMA inter-connections depending on the H7 you're using by looking at AN4891, interconnect matrix figures. 

 

[pass3master]

Thank you for your prompt response.
Thanks to you, we were able to resolve the issue.