Question regarding interrupt and memory barriers

[Tahm_A]

Hello, 

I have a kind of general question about the usage of interruptions and memory barriers.

Because of the pipeline architecture of the processor, it is recommanded by ARM (https://support.arm.com/documentation/dai0321/a/ ) to use DSB / ISB instruction when enabling disabling instruction. The guide focuses (amongst othr cases) on the NVIC operations. The CMSIS functions __NVIC_DisableIRQ and __NVIC_EnableIRQ look to respect the guidelines.

However, I’m wondering if such practices should be applied when enabling/disabling the peripheral interrupt (typically via the enable interrupt register) ? Same with the RegisterCallback functions avaialble in the HAl libraries.

 

Regards.

 

[TDK]

There’s no one size fits all rule here. In general, disabling or enabling interrupts does not necessitate a data or instruction barrier. You would only need one if you are doing something that requires the change to have taken effect. For example, you will see them prior to entering low-power modes for this reason.

[Tahm_A]

What do you mean by “You would only need one if you are doing something that requires the change to have taken effect” ? Could you elaborate ?

[TDK]

I did elaborate with the low power example. What are you having trouble with?