Question about DMA usage from STM32F0x1 reference manual

[hexiaole]

Hi friends from community. I have a question about the paragraph about DMA section from STM32F0x1 reference manual page 200, as showed below:

I don't know how to understand the red highlight part of above picture,

why there says <these ‘memory’ register, field and bit are used to define the source peripheral in peripheral-to-peripheral mode>, 

rather than <... in memory-to-memory mode>?

or <... in memory-to-peripheral mode>?

or <... in peripheral-to-memory mode>?

I can not get the point where the author want to tell me from the red highlight part of above picture.

 

[Andrew Neil]

I think they're saying that it's just an address - it can be either a peripheral or a memory address.

The fact that the register name, DMA_MARx, has 'M' in it doesn't restrict it to only Memory addresses;

Similarly, the fact that the register name,  DMA_PARx, - has 'P' in it doesn't restrict it to only Peripheral addresses. 

 

[Tesla DeLorean]

I would concur.

On platforms with DMA1 and DMA2 there's typically an expedited or parallel path into APB1 or APB2 respectively from the "peripheral" side, ie from DMAx into something within APBx, so that it requires less cycles than a full pair of load and store operation, as in the case for memory-to-memory operations, where two distinct phases / operations have to occur.