Quad SPI on STM32F4/F7

[pedro23]

Posted on September 26, 2016 at 15:20

Hi.

I have a project working with a STM32F2/F4. I want to upgrade this project a bit, adding a CPLD/FPGA to do certain tasks that actually is doing the micro.

We have done a small test and it worked with a SPI and a CPLD... but we would like it faster.

We have the option to send from several SPIs or use QUADSPI, logically QUADSPI would be better, but  reading the docs it seems oriented to work with Flash Memories, I dont know if it is possible to transmit your own data.

Is it possible to use QUADSPI like SPI, just using DMA and transfering a long block of data to the output, sending hi/low nibble alternatively?.

Best Regards.

[Tesla DeLorean]

Posted on September 26, 2016 at 17:38

Not sure about writing. Reading would seem to require you just to emulate enough of the support FLASH/EPROM protocol.

Could you use an SDIO based interface? How about a condensed FSMC one?

Inbound parallel data, look at DCMI

[pedro23]

Posted on September 27, 2016 at 10:06

Hi clive1, thanks for the ideas.

What we need is just writting. Send info at max speed to the CPLD and nothing to read, only one way (not bidirectional). If we had to simulate any hardware then it is not a good option because we need it cheap (we would need a CPLD or a FPGA more expensive).

Simulate SD would be the same probably and DCMI is for reading and I just want write.

Reading DM00124865 pdf on QUADSPI section:

''The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes''

but checking the ports used it only uses CLK, 4 DATAs and a CE. So all is based in comunications (commands, addresses and data transfered). Probably too complex for a CPLD.

Anyways the is a specific document for QUADSPI DM00227538 , reading it at the moment. Maybe we can set a certain address and then write or something like that. The idea is transfer a buffer to the QUADSPI as I said, and the size is small (1280-2500 bits), but transfered a lot of times/second

[pedro23]

Posted on September 27, 2016 at 10:35

It is very interesing the last document. It is probably easier that i tough, at least if i use the Flexible Frame Format

http://www.st.com/content/ccc/resource/technical/document/application_note/group0/b0/7e/46/a8/5e/c1/48/01/DM00227538/files/DM00227538.pdf/jcr:content/translations/en.DM00227538.pdf

Chapter 2.1 (page 13/87) 

It sends a instruccion byte, then 4 bytes address, a dumy byte and the info.

Ignoring the first n clocks after a transfer (2 x 1+4+1 = 12) i would access to the data. I would make it a bit more ''intelligent'' processing at least the instruction byte (i would use 2 instruccions, one for configuring, and another for normal process).

If  i'm not wrong this would work.

[mark239955_stm1]

Posted on September 27, 2016 at 14:07

Without putting any effort into PCB routing, I'm getting around 6.5MHz write speed between an F407 and an FPGA using the FSMC with separated 16-bit address and data buses, i.e. over 100Mbps of data throughput.  There's no mucking around with the peculiarities of a peripheral like SDIO or QSPI, (SDIO is quite fiddly; I haven't used QSPI so can't comment), and it scales from 1-byte operations to bulk data via memory-to-memory DMA transfers.

[markus239955_stm1_stmicro_com]

Posted on September 28, 2016 at 16:54

Use block RAM inside of the CPLD/FPGA to create dual Port SRAM, attach the STM32 via FSMC in SRAM or i80/LCD mode, fastest connection possible and easy to use.

Best regards,

Markus.