QSPI missing first nibble

[Arnon]

Hi

I am using the STM32F723 to read FPGA with the (notorious) QSPI interface in a custom board.

The QSPI is configured to indirect read mode, 4 bits, using DMA.

The issue is that the first nibble is not read. All other bytes are as expected.

The Errata sheet, section 2.4.1 says “First nibble of data not written after a dummy phase�?. But I am using it in read mode with no dummy phase.

The workaround, adding alternate bytes, does not solve the issue.

Changing number of bytes read each time and clock speed also had no effect.

Is it possible that this issue manifest itself in other configurations? Did anyone here experience this?

TIA,

--Arnon

#QSPI​ #[STM32 MCUs]​ 

[Amel NASRI]

Hi @Arnon​,

In read mode, it is required to have at least one dummy cycle in order to switch the data signals from output mode to input mode.

This is what we say in the specification (See RM0431 page 350):

Please check this way and keep us informed if this resolves your issue or you still have problem.

-Amel

[Arnon]

Thank you @Amel NASRI​ for taking the time to reply.

1. I have tried adding alternate bytes per the Errata sheet, no success.
2. Please note that no "turn around" is required as the interface is used in one direction (input) only. For future use, I have added in the custom board an additional I/O to indicate read\write operation. This I/O is set before the QSPI is used. In other words, each time the QSPI is used it is either input or output.

The intermediate solution i did is changing the FPGA code so the first byte is sent twice. in each QSPI event, n bytes are read, the QSPI callback function copies only the last n-1 bytes. This obviously degrade the throughput (memcpy n bytes each time, additional byte is sent)

I can try the dummy cycle but i expect the same results as the alternate byte one.

Is there a better solution?

Does ST going to address this bug?

thanks,

--Arnon

[Tesla DeLorean]

>>Does ST going to address this bug?

I wouldn't expect ST to refresh the IP on the F7 designs.

The critical path here is that it works with QSPI NOR Flash in normal use-cases.

In these, the address needs time to decode, and data buffers prefetch, before read streaming the data.