Pull up /Pull down of GPIOs in STM32F427VGT6.

[AThom.17]

Hi,

Could you please let me know the default state(Pull up /Pull down) of GPIOs in STM32F427VGT6. Especially I need to know the default state of GPIOs PC4, PB10, PA7 inorder to verify the strapping options for an external Ethernet phy interface. Iam interfacing KSZ8041NLI (ETH phy , Microchip technology) with STM32F427VGT6 using MII interface. For proper working of PHY i need to set the strap option properly. Kindly reply me as soon as possible.

[Uwe Bonnes]

Have a look at the reference manual, especially for exceptions. For F427, if I remember well, default pin state is input, no pull.

[Tesla DeLorean]

Sounds like the design expected external pull up/down option.

​

Pins float until configured.​

[waclawek.jan]

> Pins float until configured.​

Except the JTAG pins.

THe RM0090 GPIO chapter is quite clear in this regard.

JW