problem with TIM exception stm32f103

[FEkic]

So I just started to use stm32f103 MCU that I have but for some reason I code doesn't go into the TIM2_IRQHandler.

This is my code:

.thumb
 .syntax unified
 .equ GPIOB,0x40010C00
 .equ RCC ,0x40021000
 .equ TIM2 ,0x40000000
 .equ NVIC ,0xE000E100
 .global main
main:
 ldr R0,=RCC
 mov R1,0b1000
 str R1,[R0,0x18] //set the GPIOB Clock || RCC_APB2ENR
 mov R1,0b1
 str R1,[R0,0x1C] //set the TIM2 Clock || RCC_APB1ENR
 
 ldr R0,=TIM2
 mov R1,0
 str R1,[R0,0x28] //set the prescaler to 0 || TIM2_PSC
 mov R1,255
 str R1,[R0,0x2C] //set the ARR to 255 || TIM2_ARR
 mov R1,0b01
 str R1,[R0,0x0C] //enable the interrupt || TIM2_DIER
 str R1,[R0] //enable the counter || TIM2_CR1
 
 ldr R0,=NVIC
 ldr R1,=0x10000000 //position of TIM2 in NVIC
 str R1,[R0] //Enable the global TIM2 interrupt
 
 ldr R0,=GPIOB
 ldr R1,=0x44444424
 str R1,[R0,0x04]
wow:
 nop
 b wow
.global TIM2_IRQHandler
TIM2_IRQHandler:
 ldr R0,=GPIOB
 ldr R1,[R0,0x0C] //read the output of GPIOB || GPIOB_ODR
 ands R1,0b1000000000
 mov R1,512
 ite ne
 strne R1,[R0,0x14]
 streq R1,[R0,0x10]
 ldr R0,=TIM2
 mov R1,0b00
 str R0,[R0,0x10]
 
 bx lr

[waclawek.jan]

> I can't get the TIM exception to work

And what are exactly the symptoms? GPIO does not toggle? That might mean several things - timer does not run, timer runs but interrupt does not fire in NVIC, interrupt fires but does not run the ISR handler (e.g. if it is not correctly put in the vector table); code may even hang in the startup code. You need to distinguish them.

Use disassembler to check the ISR address is properly set in the vector table. Use debugger, read out and check the TIM2 registers. Make sure TIM2->CNT changes.

JW

[FEkic]

I have made sure that TIM2->CNT works but the code doesn't enter the exception

[waclawek.jan]

I listed several things to check.

JW

[JayD]

With this line:

str R1,[R0,0x0C] //enable the interrupt || TIM2_DIER

You have set the CC2IE & CC3IE, but it seems you have not write any value in TIM2->CCR2.

I suggest that you active the UIE (TIM2 update interrupt) and see if the it trigger TIM2_IRQHandler at TIM2 counter rollover.

[FEkic]

I checked and the code does set the UIE bit

[Tesla DeLorean]

1. ldr R0,=TIM2
2. mov R1,0b00
3. str R0,[R0,0x10]

Should be STR R1,[R0,0x10] ; TIM_SR, and done earlier so it clears the pipeline before the tail-chain test

[FEkic]

Whoops didn't realize that thank you pointing out my mistake