Problem with PLL

[frederic239955_st]

Posted on October 26, 2010 at 11:39

Problem with PLL

[Tesla DeLorean]

Posted on May 17, 2011 at 14:12

Perhaps you should program the flash system to the correct wait states for the final operating speed BEFORE switching to it. This is also true for ALL the bus dividers and prescalers, so they don't clock outside their bounds.

You should check that the system is using the correct source BEFORE proceeding.

Look at the PLL setting code in the library for various speeds. EXAMPLE below

/*******************************************************************************

* Function Name  : RCC_Configuration

* Description    : Configures the different system clocks.

* Input          : None

* Output         : None

* Return         : None

*******************************************************************************/

void RCC_Configuration(void)

{

  /* RCC system reset(for debug purpose) */

  RCC_DeInit();

  /* Enable HSE */

  RCC_HSEConfig(RCC_HSE_ON);

  /* Wait till HSE is ready */

  HSEStartUpStatus = RCC_WaitForHSEStartUp();

  if(HSEStartUpStatus == SUCCESS)

  {

    /* Enable Prefetch Buffer */

    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);

    /* Flash 2 wait state */

    FLASH_SetLatency(FLASH_Latency_2);

    /* HCLK = SYSCLK */

    RCC_HCLKConfig(RCC_SYSCLK_Div1);

    /* PCLK2 = HCLK */

    RCC_PCLK2Config(RCC_HCLK_Div1);

    /* PCLK1 = HCLK/2 */

    RCC_PCLK1Config(RCC_HCLK_Div2);

    /* ADCCLK = PCLK2/4 */

    RCC_ADCCLKConfig(RCC_PCLK2_Div4);

    /* PLLCLK = 8MHz * 7 = 56 MHz */

    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7);

    /* Enable PLL */

    RCC_PLLCmd(ENABLE);

    /* Wait till PLL is ready */

    while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)

    {

    }

    /* Select PLL as system clock source */

    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

    /* Wait till PLL is used as system clock source */

    while(RCC_GetSYSCLKSource() != 0x08)

    {

    }

  }

/* Enable peripheral clocks --------------------------------------------------*/

  /* Enable DMA1 and DMA2 clocks */

  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE);

  /* Enable ADC1, ADC2, ADC3 and GPIOC clocks */

  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 |

                         RCC_APB2Periph_ADC3 | RCC_APB2Periph_GPIOC, ENABLE);

}

[frederic239955_st]

Posted on May 17, 2011 at 14:12

Hello,

thanks for helping.

For now, I simply put HPRE to 1000 to test (AHB clock to SYSCLK/2) and it works.

Looks like you're right. I'm going to look at these wait states right now, and I come back to give some news.

Edit: I put 2 wait states and put back AHB Clock to 72MHz, it's OK....Thanks again