Problem regarding programming NOR flash via OCTOSPI

[JohnG]

I am using STM32L4R5 and S25FL128L (quadspi) NOR flash interfaced over OCTOSPI. Currently we are using single channel for erase, read and write operations. Read and erase operations seems working fine. But we are facing issue for write/program operations.

When we use indirect mode STM32L4R5 is able to write only 2 bytes instead of 256 bytes for one program command. If we use memory mapped mode, we able to write only 32 bytes in one loop of 256 byte write.

Could you please provide your expert comments for this issue.

[Andreas Bolsch]

I've used a Nucleo-l4r5zi board with two W25Q128 chips in dual-single and dual-quad mode, no problem encountered in memory mapped read and indirect read/program/sector erase/mass erase. Works almost in almost the same way as QuadSPI, only minor changes required. The source code (assembler) is available here:

http://openocd.zylin.com/#/c/4321/

[AVI-crak]

QUADSPI-> CR | = _VAL2FLD (QUADSPI_CR_FTHRES, 7); // FIFO threshold level 8Bute

In read mode, gives the dma command about data availability, dma should use its FIFO to read / write 8Bute for one win of the data highway arbiter.

In the recording mode, gives a command about the free space in the FIFO of 8Bute size.

The time it takes dma to access the memory MK - may be higher than 16 system clock cycles. If you read / write in small portions - there will be a pass.

The S25FLxxx series cannot operate normally at frequencies below 50Mgz. At the time of recording, it is impossible to free the chip select line, or to stop the tact line. Data for recording is transmitted in one large packet.

Order: Write Enable (06h), Read Status Register-1 ! (WEL = 1) (WIP = 0), Page Program (02h), Read Status Register-1 ! (WEL = 0) (WIP = 0), end.