priority grouping

[guyvo67]

Posted on October 28, 2009 at 11:29

priority grouping

[guyvo67]

Posted on May 17, 2011 at 13:27

Hi,

As this topic still confuse me a bit maybe you guys can help me get ride of it ;)

In the case of eg STM32F103RET there are 4 bits implemented as interrupt priorities. ( In theory this arm core can have up to 8 bits ) Which means that I have 16 different levels of priorities. Suppose that I don't want to have sub-priorities and want to work with the full 16 levels of pre-emption only, are the following assumptions correct:

7 6 5 4 3 2 1 0

x x x x 0 0 0 0 (-> 4 lowers always zero )

group 0 : preemption [7-1] sub [0]

--> according to the book ''definitive guide to arm cortex page 120'' this could not be implemented depending on the core, is this the case with ST devices ?

group 1 : 7.1 indicates seven bits of pre-emption priority, one bit of sub priority ( out of technical reference manual )

So if I take group 1 in the case of 4 bits priority implemented I have only 16 level of pre-emption and none sub levels ?

So in fact group 1 until 4 will have the same impact. As soon as I'll take group 5 I will have 8 level of pre-emptions and 1 sub level and so on correct ?

Thanks

-G

[guyvo67]

Posted on May 17, 2011 at 13:27

Ok thanks,

So if I got it well pri-group 4 is the minimum we can set for ST device according the document so having only 16 pre-emptions without sub-pri isnt't possible as we can see in the binary point mask:

group 4 0b100 0bxxx.y [7:5] [4] 8 2

group 5 0b101 0bxx.yy [7:6] [5:4] 4 4

group 6 0b110 0bx.yyy [7] [6:4] 2 8

group 7 0b111 0b.yyyy None [7:4] 1 16

Out of the comment from NVIC_PriorityGroupConfig in the nvic file which is not what's in that document ( v2 :(

- NVIC_PriorityGroup_0: 0 bits for pre-emption priority 4 bits for subpriority

- NVIC_PriorityGroup_1: 1 bits for pre-emption priority 3 bits for subpriority

- NVIC_PriorityGroup_2: 2 bits for pre-emption priority 2 bits for subpriority

- NVIC_PriorityGroup_3: 3 bits for pre-emption priority 1 bits for subpriority

- NVIC_PriorityGroup_4: 4 bits for pre-emption priority 0 bits for subpriority

Out of the main.c interrupt priority example file which follows the comment above:

/* Configure one bit for preemption priority */

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);

So it's still not clear to me because the document doesn't say anything of pri-group 0-4 while the source code does. But there's a lot of shifting done in the NVIC init code I saw like:

tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;

tmppre = (0x4 - tmppriority);

tmpsub = tmpsub >> tmppriority;

.....

Maybe this is the reason why the grouping isn't quit like the specs tell us. I didn't go into details (debug) to finger it out.

-G

[ This message was edited by: guyvo67 on 26-10-2009 12:50 ]

[ This message was edited by: guyvo67 on 26-10-2009 18:55 ]

[16-32micros]

Posted on May 17, 2011 at 13:27

Hi,

You can refer to STM32 Implementation of the Cortex-M3 in this document ''STM32F10xxx Cortex-M3 programming manual''

PM0056 -

http://www.st.com/stonline/products/literature/pm/15491.pdf

Cheers,

STOne-32.

[tomas23]

Posted on May 17, 2011 at 13:27

ST-One, I agree that Library 3.0 is much more confusing than 2.0, because it doesn't offer any parameter combinations or options for subpriority.