Phantom Flash Errors

[maroot]

Posted on October 31, 2014 at 13:53

Hi all.

I'm working on a project on an STM32L151CBT6 uC, and getting occasional, unexplained error bits WRPERR and SIZERRset in the flash controller. I set up the flash error interrupt to use the highest priority group so as to preempt other interrupts, and found that it is happening on the same line of code every time:

dma_config->p_stream->CMAR = (uint32_t)dma_config->mem_addr;

If it matters, ^ this line is in an ISR also. 687B ldr r3, [r7, #4] 6A1B ldr r3, [r3, #32] 687A ldr r2, [r7, #4] 68D2 ldr r2, [r2, #12] 60DA str r2, [r3, #12] BF00 nop BF00 nop BF00 nop BF00 nop <----------- This ^ is the assembly for that line. I added the nops so as not to destroy the evidence. The arrow indicates where the PC is when I step out of the error ISR. r2 is the mem_addr and r3 is the address of CMAR. Everything to me looks correct and works correctly when I step through it. The strange part is that this code is being called once every 50 ms, but the flash errors only get set occasionally. Maybe 10 times per minute. So I'm stumped. Any ideas? Thanks. -MR

[Tesla DeLorean]

Posted on October 31, 2014 at 17:13

I'd start by looking at the flash prefetch and wait states with respect to clock/voltage, check the errata, and look at if the interrupt was trashing registers/stack

If you have a demonstrable failure, suggest you contact your local FAE

[maroot]

Posted on October 31, 2014 at 19:29

Thanks for the response Clive.

I've figured some things out, and have gotten the error bits to stop being set.  The problem seems to be linked to the DMA transfer itself.  The error was happening (only occasionally) during a sequence (executed every 50 ms) that looked like this:

In an ISR for an IDLE frame on the USART after a DMA transfer:

 - calculate the bytes transferred from the CNDTR register

 - Disable the DMA Channel

 - Write a new value for CMAR

 - Write the CNDTR register for the next transfer

 - Enable the DMA Channel

I expect to get 18 bytes for each transfer, and I do, *except* for the ones where the flash errors occur.  On these, CNDTR indicates that I got 19 bytes.  And the time at which the errors occur looks to be shortly after I disable the DMA channel.

I fixed the error by disabling the USART before the above sequence, and then reenabling afterwards.

Even though the problem is fixed (it seems), I'd still like to know what was happening.  Does it make sense that I was getting those errors in this situation?