Pending and disabling of interrupts in STM32L431RCT6

[STeja.1]

I am using tim6 with a period of 140 ms. In another interrupt that has a priority greater than tim6, I am disabling the tim6 interrupt. But sometimes even after disabling that interrupt, tim6 update interrupt occurs and after that, a variable is corrupted which has no relation with the code in the interrupt handler. I am not clearing pending interrupts before disabling the interrupt.

How the interrupt handler is being called after disabling?

can a pending interrupt of tim6 be called after it has been disabled?

[waclawek.jan]

> I am disabling the tim6 interrupt

How exactly?

JW

[STeja.1]

HAL_TIM_Base_Stop_IT(&htim6);

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)

{

 /* Check the parameters */

 assert_param(IS_TIM_INSTANCE(htim->Instance));

 /* Disable the TIM Update interrupt */

 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);

 /* Disable the Peripheral */

 __HAL_TIM_DISABLE(htim);

 /* Return function status */

 return HAL_OK;

}

[waclawek.jan]

That disables the interrupt it at TIM level. There's a relatively long path from timer to NVIC, and even if you disable it at the timer, it takes time until the "interrupt removed" signal reaches NVIC (this is in fact the same problem as this).

Maybe moving the interrupt disable up in the higher-priority interrupt code would help, but this is something not trivial to make 100% reliable.

A foolproof way is to disable TIM6 interrupt at NVIC level.

JW

[STeja.1]

But what is the relation between timer interrupt and data corruption? And what if I clear the pending interrupt before disabling the interrupt does it solve the problem?

[Piranha]

Let's suppose the other higher priority interrupt is for some EXTI line.

1. TIM6 ISR starts execution.
2. EXTI ISR interrupts the TIM6 ISR.
3. EXTI ISR disables TIM6 interrupt.
4. EXTI ISR finishes execution.
5. TIM6 ISR continues execution from where it was interrupted.

The result - you've got TIM6 interrupt disabled but ISR still running. You can solve this by either making both interrupts the same priority or implementing a critical section in TIM6 ISR and related code, which either disables the EXTI interrupt in NVIC or disables all interrupts on CPU (PRIMASK register).

[waclawek.jan]

> But what is the relation between timer interrupt and data corruption?

How could I possibly know? This is your code.

Try to place a data breakpoint (a.k.a. watchpoint) at the variable in question, that should reveal which part of code overwrites it (unless it's mismanaged DMA).

JW