Output port voltage vevel in STM32F4

[foruvarov]

Posted on May 17, 2013 at 12:33

Hello!

Could anybody explain how to know the actual output voltage level for STM32F4?

According to the datasheet, all I/Os are TTL and CMOS compliant, but there is no information about how actual value is derived. E.g., for VDD 3.3V output level could be 2.4V (CMOS) or 2.9V (TTL).

I suppose it is dummy question, but I need to be sure.

Does anybody know something on this subject?

#cmos #stm32 #output-level #ttl

[waclawek.jan]

Posted on May 17, 2013 at 13:03

Datasheet, Table 47.

JW

[foruvarov]

Posted on May 18, 2013 at 19:43

Thanks a lot, Jan!

I've already saw this table. And as I said before, according to the table output voltage could have two different values of logical ''1'' (VDD=3.3V): 2.9V for TTL logic or 2.4V for CMOS logic.

Maybe my question is not clear. I can't understand how does MCU ''know'' what kind of logic is connected to pin's output. And hence I can't define the exact value of output voltage.

Could you define it?

[jj2]

Posted on May 18, 2013 at 20:47

We have - but have not yet, ''fired-up'' STM32F4 demo boards - but strongly suspect that GPIOs will output logic ''1'' w/in few hundred mV of VDD.  (our quality Tek scope confirms that on each/every M3 and M0 we've built/tested/shipped)

That level is sufficient to be ''seen'' as logic ''1'' by either cmos or ttl device - in ''most'' conditions.  (cmos must be confined to 5V VDD or less - older CMOS may operate from far higher VDD (we've used 12V) and voltage shifters must be employed - in such case)

And - as Clive has recently noted - surest, most convincing ''proof'' is your live ''test/experimentation'' - but insure that any/all voltage levels fed back to STM32 are w/in written spec.

[waclawek.jan]

Posted on May 18, 2013 at 22:24

The chip does not select CMOS or TTL in any way. This is only a clumsy way to say that it's compatible with both. Read it this way: while Vcc is within the given boundaries, and with given load, the output levels conform to both CMOS and TTL.

Although confusing, manufacturers sometimes write datasheets in this form to avoid questions like ''and will this interface to standard TTL?'' from some of the stup^H^H^H^Hless experienced users. For example, quite often for chips with I2C interface, you can see in datasheets a table with timing for both 100kbps and 400kbps, while the chip is simply 400kbps capable which implies that it is also 100kbps capable.

JW

[foruvarov]

Posted on May 20, 2013 at 12:19

Thanks to all!

Answer was simpler than I thought.