OSPI Default Pin Level of DIO0-3 in QSPI mode

[Jurni_JasteD]

Dear Community,

for my application I'm using a STM32H723VGTx to control a sensor via the OSPI interface which is operating in QSPI mode (STM32 master, sensor slave). After I had a look on the bus interface with a Logic Analyzer I'm wondering, if there is a OSPI/QSPI parameter to leave the data pins DIO0-3 on a High level after the transmission is finished as there is for the CLK (HAL_OSPI_CLOCK_MODE_3)?

I would like to have a QSPI behavior like this (shown in turquoise):

Thank you in advance!

Best regards,
Jurni_JasteD

[Andreas Bolsch]

The interface is designed with memory (flash, EEPROM, ...) in mind, and for these the level on data pin is don't care as soon as CS goes inactive. So, no, except that you could activate the pull-ups/pull-downs to prevent the data pins from floating.

[Jurni_JasteD]

Hello @Andreas Bolsch,

thank you for your answer!
Then I need to check if I can handle the pin levels via pull-up/pull-down resistors to match my application conditions.

One further question you might can help me: Do you know if there is a MCU in the in the upper performance series like STM32H7 or STM32F which are capable to configure the OSPI/QSPI DIO pin levels like I have mentioned?

Best regards,
Jurni_JasteD

[KDJEM.1]

Hi @Jurni_JasteD ,

The OctoSPI interface support also QuadSPI memories. OctoSPI interface is fully configurable and supports two, four or eight data lines:

• Single-SPI (traditional SPI)
• Dual-SPI
• Quad-SPI
• Octo-SPI

For more information about the DIO pins configuration of OSPI/QSPI, you can have a look to Application note AN5050 and precisely OCTOSPI GPIOs and clocks configuration Section. This section can help you to configure the OCTOSPI interface with different mode such Quad-SPI mode.

I hope this help you!

Kaouthar