Openocd

[Hedley]

I ported openocd to the stm32l522. ​

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https://github.com/morbos/openocd-0.10.1

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openocd -f board/st_nucleo_l522.cfg​

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From there you can remote connect from gdb, flash, and see the s/ns processor regs. Watchpoints work also.

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Hedley​

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[TarekB-ST]

Nice!

I suggest to post your change into the official OpenOCD repository.

There a whole gerrit to review changes at: http://openocd.zylin.com

By the way, for STM32L5 there is already an existing change at : http://openocd.zylin.com/#/c/5344

You can try to find a consensus with the owner of the change, if you judge that your change is more appropriate.

Happy New Year !

Tarek

[Hedley]

Hi Tarek,

Appreciate the code ptr. That version supports L5 as a new flash target. I do also. The missing piece is ARMv8m support. I handle the secure and non secure contexts. That also involved a change to the STlink hla code to make it ARMv8m aware.

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Enjoy the Festive Season​!

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Hedley

[Hedley]

I updated the openocd me. It's st_nucleo_l552.cfg dunno why I have been typoing that as 522...

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The new version also supports correct flash size reading and flashing when the watermarks are used. ​before, if you watermark the S/NS split, the erase fails at the watermark address. The soln I found was to temporarily unlock the option bytes and default the watermarks, I dont permanently write them, it's just for the curr reset. Next time you reset, the old values take over.

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I have 2 Ada programs running on the stm32l552. The first part of the flash at 0C000000 is S, then at the watermark, the NS program begins at 0802xxxx.

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There is no ST sample code so I had to do this blind with just the RM and SVD file + prior L4 ports.​

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github.com/morbos/STM32/tree/master/L/L552/sx1276_rom_l552​