On the STM32U5xx, keep ADCx->CCR PRESC = 0, do not use the prescaler.

[_andreas]

I'm using the ADC1 and ADC4 with PLL as kernel clock (MSIS 24MHz pll'ed to 32768 Hz watch crystal / 2 x (11 + 2163/8192) / 24) = 5.632 MHz).

The ADC1 in combination with the MDF "looses" every second sample.

The ADC4 never gets ready.

The errata sheet (https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/70/0e/1e/74/c5/d2/4d/95/DM00648236/files/DM00648236.pdf/jcr:content/translations/en.DM00648236.pdf)

mentions that you can use prescaler values greater 0 when not using the ADCs at the same time. But there seem to be more conditions when the prescaler value will interfere.

[CMYL]

Hi @_andreas

Do you mean errata 2.9.1 ADC4 conversion error when used simultaneously with ADC1?

If yes, d the ADC4 clock duty cycle must be set to between 45% and 55%.  The PLL division must be set to an even division (division by 2, 4, and so on) to guarantee a 50% ratio. This is according to the workaround.

I see that this is the case in your pll2_r_ck divisions, but can you check with HSI16 as source clock for both ADCs to be sure that not the issue is not related to that duty?

BR,

Younes

[_andreas]

Why should it be related to the duty cycle? And why should it not be around 50% when I use an even divider?

[_andreas]

@Younes LAHBIB​ I've described the setup as compact as possible, if you need more help to reproduce it, just write me. But I'm not going to invest more time, it took me far too long already to pin it and find a work around.