On STM32U575, RAMCFG_MxCR bit ECCE not set on start up with FLASH_OPTR bit SRAMx_ECC 0 (enabled)

[PScal]

I managed to program the FLASH_OPTR user option bytes and set the SRAM2_ECC to zero (enabled). But when restarting the µC the RAMCFG_M2CR ECCE bit is not set and the RAM ECC is not active. So during startup when the .data section is initialized in SRAM2 the ECC is not active. And Activating it later directly leads to constand ECC single error interrupts and ECC double error interrupts, when reading RAM constant that was initialized before the ECC activation.

What do I oversee so that the ECC is not activated on restart?

[PScal]

Dear all,

after starting a support ticked and with the help of the support, we found out that I had the CubeMX RAMCFG active no matter how I set the ECC option there, it first resets the ECCE bit and then depending on the setting restarts the ECC. (I also had the wrong option, so that it did not restart the ECC.)

I will find a workaround to use a RAMCFG initialization that does not touch the ECCE bit.

best regards

Peer