NVIC - Defining software interrupt

[mailmail9116]

Posted on August 08, 2013 at 08:37

Hi ,

I want to add a new interrupt to the system , i know that the NVIC can support up to 256 interrupts , currently in my evaluation boad ( stm32f4g-eval) there are only 81 used .

So i added a new one here :

.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */

.word USART6_IRQHandler /* USART6 */

.word I2C3_EV_IRQHandler /* I2C3 event */

.word I2C3_ER_IRQHandler /* I2C3 error */

.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */

.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */

.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */

.word OTG_HS_IRQHandler /* USB OTG HS */

.word DCMI_IRQHandler /* DCMI */

.word CRYP_IRQHandler /* CRYP crypto */

.word HASH_RNG_IRQHandler /* Hash and Rng */

.word FPU_IRQHandler /* FPU */

.word TTS_IRQHandler /* 070813 - TTS IRQ Handler */ < - the new one , his id will be 82

Also added weak aliasing just in case :

.weak OTG_HS_EP1_IN_IRQHandler

.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler

.weak OTG_HS_WKUP_IRQHandler

.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler

.weak OTG_HS_IRQHandler

.thumb_set OTG_HS_IRQHandler,Default_Handler

.weak DCMI_IRQHandler

.thumb_set DCMI_IRQHandler,Default_Handler

.weak CRYP_IRQHandler

.thumb_set CRYP_IRQHandler,Default_Handler

.weak HASH_RNG_IRQHandler

.thumb_set HASH_RNG_IRQHandler,Default_Handler

.weak FPU_IRQHandler

.thumb_set FPU_IRQHandler,Default_Handler

.weak TTS_IRQHandler

.thumb_set TTS_IRQHandler,Default_Handler

And offcourse added a function that will handle the interrupt :

void TTS_IRQHandler(void)

{

}

Then from main i do the following steps :

NVIC_SetPriority(82,100);

NVIC_EnableIRQ(82);

NVIC_SetPendingIRQ(82);

And nothing happens , but doing the same thing on one of previously defined interrupt handler (for example :

FPU_IRQHandler

) , i really do receive the interrupt as expected , what i am missing here ?

Thanks

Michael

[waclawek.jan]

Posted on August 08, 2013 at 09:20

> i know that the NVIC can support up to 256 interrupts

Where do you have this information from?

NVIC as an IP component can support up to 256 interrupts, but NVIC as implemented in STM32F40x/41x supports 82 interrupts.

JW

[mailmail9116]

Posted on August 08, 2013 at 10:14 Yes you are correct , i was looking into the General Cortex M4 guide . but when looking into the reference guide of the evaluation board , i still see that i can use up to 86 interrupts (STM32F407IG) and now only 81 is currently used , so it should work .

82 maskable interrupt channels for STM32F40x and STM32F41x, and up to 86<
br
>maskable interrupt channels for STM32F42x and STM32F43x (not including the 16<
br
>interrupt lines of Cortex™-M4F

Thanks Michael

[waclawek.jan]

Posted on August 08, 2013 at 10:51

As yourself quoted it:

 > 86 
maskable interrupt channels for STM32F42x and STM32F43x

so it's 82 for the '407 you are using. And they are numbered 0.. JW