NUCLEO-H7S3L8 USB_OTG_HS Host Issue: TXERR during EP0 SETUP

[wooseong]

I am currently using the NUCLEO-H7S3L8 CN2 Type-C port as a USB_OTG_HS embedded PHY host/source.

The TCPP03 source path opens successfully, and both the USB stick attachment and port reset are working. After the reset, HPRT reads 0x00001005, which seems to indicate speed=HS and that the port is enabled.

However, during the first EP0 SETUP GET_DESCRIPTOR request:

• HAL_HCD_HC_SubmitRequest() = HAL_OK

• HAINT = 0x00000001

• HCINT = 0x00000080

• TXERR = 1

• xfer_count = 0

The exact same issue occurs even during a raw HAL EP0 smoke test, prior to involving USBX/FileX.

I would like to verify the following points:

1. What is the mandatory clock/power initialization sequence when using the USB_OTG_HS embedded PHY host on the H7S3L8?

2. Is it acceptable to use HSI → PLL3Q for the USBPHYC clock, or is an HSE strictly required?

3. What are the necessary settle/wait conditions after enabling USBHSREG?

4. Are there any required CC/UCPD configurations for the CN2 Type-C/TCPP03 source setup, apart from the PM9 PWR_EN + TCPP03 provider gate?

5. Is the state where HPRT = 0x00001005 and HCFG = 0x00000201 considered normal under these conditions?

[wooseong]

Update:

I tested the USBPHY reference clock and USB HS regulator related points suggested by similar H7RS/N6 USBPHYC issues.

Current HSI -> PLL3Q -> USBPHYC path:

• USBPHY clock source: PLL3Q

• USBREF forced/logged as 24 MHz

• CCIPR1 = 0x00002a40

• USBPHYCSEL = 0x00002000

• USBREFCKSEL = 0x00000a00

• USBHSREGEN = 1

• USB33RDY = 1

• GOTGCTL after HAL_HCD_Start() = 0x002c0000

However, the first EP0 SETUP still fails with:

• HAINT = 0x00000001

• HCINT = 0x00000080

• TXERR = 1

• xfer_count = 0

I also tested HSE-based USBPHYC clock presets.

HSE preset:

• HSERDY = 0

• PLL3RDY = 0

• USBPHYC clock setup failed with HAL status 0x03

HSE bypass preset:

• HSERDY = 0

• PLL3RDY = 0

• USBPHYC clock setup failed with HAL status 0x03

So I could not yet verify USBPHYC using the board HSE. The current working-but-failing path is still HSI -> PLL3Q -> USBPHYC 24 MHz, where the first EP0 SETUP fails with TXERR.

According to UM3276, the NUCLEO-H7S3L8 default HSE source should be the on-board 24 MHz X1 crystal. Is there any board revision, solder bridge, boot configuration, or power condition that would make HSERDY stay 0 on a default NUCLEO-H7S3L8?

Also, is HSI -> PLL3Q -> USBPHYC 24 MHz expected to be reliable enough for USB_OTG_HS embedded PHY host mode, or should HSE be considered mandatory in practice?