Solved
No interrupt on tmr overflow
Posted on March 20, 2017 at 20:10
STM32F437
I am using TIM4 for input capture and an interrupt occurs when external events occur. However I stopped the external event and no interrupt occurs on overflow although the UIF bit is set in SR. Code snippet below and TIM4 is listed below that.
Thank you,
JH
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void RpmTask(void *p_arg)
{ TIM_TypeDef *tim4 = TIM4; RCC_TypeDef *rcc = RCC; OS_ERR err; uint16_t rpm4 = 0;NVIC_InitTypeDef NVIC_InitStruct;
/*Interrupt packet initialization*/ NVIC_InitStruct.NVIC_IRQChannel = TIM4_IRQn; NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0; NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStruct); //RPM timer setups // APB1PeriphClock - 42 MHz // APB2PeriphClock - 84 MHz RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM9, ENABLE);TIM_TimeBaseInitTypeDef tim4_base;
tim4_base.TIM_Period = 0xFFFF; tim4_base.TIM_Prescaler = 0; //42000 -1; tim4_base.TIM_ClockDivision = TIM_CKD_DIV1; //digital filter clk div, don't care, filtering is off tim4_base.TIM_CounterMode = TIM_CounterMode_Up; tim4_base.TIM_RepetitionCounter = 0; //t1&t8 pwm, don't care TIM_TimeBaseInit(TIM4, &tim4_base);TIM_ICInitTypeDef tim4_icInit;
tim4_icInit.TIM_Channel = TIM_Channel_1; tim4_icInit.TIM_ICPolarity = TIM_ICPolarity_Rising; //r, f, both tim4_icInit.TIM_ICSelection = TIM_ICSelection_DirectTI; //dir, ind, trc tim4_icInit.TIM_ICPrescaler = TIM_ICPSC_DIV1; //1-8 tim4_icInit.TIM_ICFilter = 0x0; TIM_ICInit(TIM4, &tim4_icInit); TIM_UpdateDisableConfig(TIM4, 0); /* Enable the CC2 Interrupt Request */ TIM_ITConfig(TIM4, TIM_IT_CC1, ENABLE);/* TIM enable counter */
TIM_Cmd(TIM4, ENABLE);uint16_t cnt = 0;
while(1) { cnt = TIM_GetCounter(TIM4); OSTimeDlyHMSM(0u, 0u, 0u, 1000u, OS_OPT_TIME_HMSM_NON_STRICT, &err); }}void timer4_isr(void)
{ volatile int optimizerBlock = 0; TIM_TypeDef *tim44 = TIM4; uint16_t rpm4 = 0; uint32_t cnt; CPU_SR_ALLOC(); CPU_INT_DIS(); OSIntNestingCtr++; CPU_INT_EN(); if (TIM_GetITStatus(TIM4, TIM_IT_Update) == SET) { ... TIM_ClearITPendingBit(TIM4, TIM_IT_Update); } if (TIM_GetITStatus(TIM4, TIM_IT_CC1) == SET) { ... TIM_ClearITPendingBit(TIM4, TIM_IT_CC1); } OSIntExit();}Expression Value Location Type tim4 0x40000800 R5 TIM_TypeDef * CR1 0x0001 RESERVED0 CR2 0x0000 RESERVED1 SMCR 0x0000 RESERVED2 DIER 0x0002 RESERVED3 SR 0x001D RESERVED4 EGR 0x0000 RESERVED5 CCMR1 0x0001 RESERVED6 CCMR2 0x0000 RESERVED7 CCER 0x0001 RESERVED8 CNT 51557 PSC 0x0000 RESERVED9 ARR 0x0000FFFRCR 0x0000 RESERVED10 CCR1 0x00000000 CCR2 0x00000000 CCR3 0x00000000 CCR4 0x00000000 BDTR 0x0000 RESERVED11 0x0000 DCR 0x0000 0x40000848RESERVED12 0x0000 DMAR 0x0001 0x4000084C RESERVED13 0x0000 OR 0x0000 0x40000850 RESERVED14 0x0000