New I2C Master mode: Can it enforce SCL pulses to free a blocked bus?

[flyer31]

Thank you for the new I2C peripheral in STM32H7, this really looks VERY much improved compared to STM32F4.

Can the STM32H7 I2C in master mode somehow "free the bus" in case of "stupid slaves holding the SDA line down"?

It is a quite common problem of I2C slave, that if they send some data on the bus and by some error miss an SCL clock, they can "accidentially" keep the SDA line on zero indefinitely, while waiting for the "missing" SCL clock from master.

To relax such a situation, it is necessary, that the master best sends 8 SCL pulses to "Reset the bus". Is this possible in the new STM32H7 master mode? (or does it generally switch back to passive / to slave, if it recognizes that the SDA line is low?).

... in STM32F4 solving this situation was quite cumbersome ... it was necessary to release the Alternate Function of the SCL pin, then taking digital control over the SCL pin, and simulating 8 SCL pulses with approximately the I2C baud rate ... .

... If you know some other method to enforce the (STM32H7) master to send 8 SCL pulses, even if the SDA line is held in dominant state / zero value, this would be great? (or does the STM32H7 master automatically switch back to slave mode, if it recognizes a zero SDA line, as this was also the case for teh STM32F4?)

[S.Ma]

This is the error recovery, for example when the master read a memory full of 0x00 and the MCU is reset while reading data...

I would guess the error recovery still requires manual intervention as it's beyond the I2C "per se" specification. In my case, I push 9 stop bits if either SDA or SCL are not high level prior issuing a Start bit from idle bus condition.

[flyer31]

... I now checked more ... but my other info from 1 hour ago was WRONG. STM32H7 in case of failed start (due to SDA low) will NOT automatically send out these 2 SCL edges.. .

Also setting the stop condition (as you proposed) does NOT work in my case.

But I got it now in a way which is fine for me: If I set the CR1 register to zero, and then again to I2C_CR1_PE. Then somehow the SCL line will send out 2 clock cycles with the correct baud rate... this is nice ... . This should do it for me.

[flyer31]

Very nice idea, thank you ... maybe this would have worked already like this for STM32F4... I did not get this idea at this time I think.

But to my big relief STM32H7 will automatically create 2 clock pulses in case of hanging SDA (after 4 bit times SDA hanging on zero) ... this is very nice .. this should be sufficient to solve such "hanging bus problems" automatically.