NAND memory read errors

[troy1818]

Posted on January 11, 2014 at 23:08

Hello,

I will try with this forum as a last resort for my problem, namely getting my NAND memory to play with me.

http://www.ic-on-line.cn/download.php?id=1915099&pdfid=5E619D21E0C125A4A94BC1A860068896&file=0459\h27ubg8t2btr-bc_6373736.pdf

I don't have any experience with NAND before. I am using stm32f407VG with FSMC to communicate with the chip (168Mhz internal clk). My problem is reading the data on the NAND after i have programmed it.

The thing is that sometimes (approx. 0.2%) I get unexpected value. Usually it is only one bit that is wrong (0x30 instead of 0x20, 0x38 instead of 0x8, A6 instead of A2 etc.). The 0.2% is not spread out at random. The first page (8192 bytes) is correct all the time when reading. I have seem a pattern though. It seems that I get no read errors at page 0, some errors on page 1, even more errors in 2 and so on.

Also when I study one of these read errors I can see that about 50% of the time I get the correct value from the NAND memory (verified with oscilloscope). This also seems to be the case for all these problematic addresses.

These are my thoughts:

* I have tried with different blocks but I get the same problems (surely they cannot all be bad blocks??).

* I have tried with a second board with same exact problem.

* I have double and triple checked the pins/connection.

* I know that FSMC works since I can use it for other peripherals with good result (but with another bank)

* I understand the relevancy of the timing for the NAND memory and I suspected something wrong with this a long time but concluded that this is not likely my problem.

* On the same FSMC bus I have another peripheral connected (ssd1963). I have the CS for this chip always high so there should not be any problems I think? This chip is not even initialized (since I would need FSMC with other setting/bank for this).

* I am not using ECC since my board does not need to be very serious project. I just want to play around a little with NAND.

Some code:

  p.FSMC_SetupTime = 0x1;

  p.FSMC_WaitSetupTime = 0x2;

  p.FSMC_HoldSetupTime = 0xA;

  p.FSMC_HiZSetupTime = 0x1;

  FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;

  FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;

  FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;

  FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;

  FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;

  FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Disable;

  FSMC_NANDInit(&FSMC_NANDInitStructure);

  FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);

&sharpdefine NAND_BASE 0x70000000

&sharpdefine CMD_AREA (u32)(1<<16)

&sharpdefine ADDR_AREA (u32)(1<<17)

&sharpdefine DATA_AREA (u32)(0)

&sharpdefine NAND_CMD (*((volatile uint8_t *)(NAND_BASE | CMD_AREA )))

&sharpdefine NAND_ADDR (*((volatile uint8_t *)(NAND_BASE | ADDR_AREA )))

&sharpdefine NAND_DATA (*((volatile uint8_t *)(NAND_BASE | DATA_AREA )))

void hynix_read_byte_cmd(uint_32 address)

{

  uint_16 column = 0;

  uint_16 page = 0;

  uint_16 block = 0;

  uint_16 plane = 0;

  column = address & 0x1FFF; // 13 bits (don't care about the 14:th bit for ECC memory)

  page = (address >> 13) & 0xFF; // 8 bits

  block = (address >> (13 + 8)) & 0x3FF; // 10 bits

  plane = (address >> (13 + 8 + 10)) & 0x1;

  NAND_CMD = 0x00;

  NAND_ADDR = (column >> 0) & 0xFF;

  NAND_ADDR = (column >> 8) & 0x1F;

  NAND_ADDR = page;

  NAND_ADDR = ((block << 1) & 0xFE) | plane;

  NAND_ADDR = (block >> 7);

  NAND_CMD = 0x30;

}

uchar hynix_read_byte()

{

  return NAND_DATA;

}

I cant get my head around this problem. Perhaps someone with experience from NAND memories can give me some pointers on things that I need to consider.

Regards,

/rygelxvi

#nand-fsmc #nand #nand

[jpeacock2399]

Posted on January 12, 2014 at 23:39

What type of NAND are you using (single, double, triple)?  Any type of NAND requires ECC for single bit error correction, that's why it's so much cheaper and denser than NOR.  DLC and TLC cells are notorious for being unreliable, especially if you aren't careful about erase patterns.  Single level cells like on the old STM3210E eval board have very low (but non-zero) error rates.  Remember, NAND is inherently prone to errors, you ALWAYS have to do some kind of error correction.

Extremely high error rates like you show, 50%+, sounds more like hardware or something in access or cycle timing.

  Jack Peacock

[troy1818]

Posted on January 13, 2014 at 00:34

Hi Jack,

Thanks a lot for your post Jack! you really made my day :)

I am using 32Gb(4096M x 8bit)Legacy MLC NAND Flash and I guess MLC is 2 planes.

I re-soldered the memory on my board and now I think my behavior concerning the 50% read error for one cell disappeared.

So now I am happy to hear you say that NAND has a lot of these kinds of 1-bit errors. Because that is exactly what I see. Basically, all the blocks and pages that I tried to read so far has failed with about 0.04% of the cells having these 1-bit errors.

My memory can have up to 48 bad blocks that should not be used according to the manufacturer. That is fine and all,  but I never did expect to have these 1-bit error spread all over the memory.

I think I really need to consider the ECC as you say. Thanks again for letting me know !!

Regards,

rygelxvi

[jpeacock2399]

Posted on January 13, 2014 at 15:54

A single bit error is recoverable with ECC so it is not considered a bad block.  A simple ECC will typically yield 1 bit correction and two bit error detection.  With 2 bit errors then it's a bad block since you can't recover the data.

You will see higher error rates with MLC than with single cell.  Also check vendor errata about erase patterns...sometimes erasing one block will adversely affect another when using multi-layer NAND, has to do with the way the internal comparators work to decode two bits from one cell.

MLC is fine if you have aggresive ECC correction (check on variations of Reed-Solomon for larger bit lengths) and aren't worried about speed.  That's why there's a separate area for metadata in NAND ICs, plenty of room for long ECC checksums.  It's the type of NAND most often found on low end USB flash sticks, where capacity is more important than speed or error rate.

  Jack Peacock

[troy1818]

Posted on January 13, 2014 at 17:08

Hi Jack,

Yes, after reading more on the subject it seems to be a lot of trouble with NAND. Not only erase but read operation seems to tear the memory in other cells, after about 100.000 read you need to erase that block and write the data again. Also evening out r/w/e operations on the cells seems to be quite important.

I'm lucky that my project is just spare time stuff, otherwise I would consider another memory tbh.

I will look into the mechanics of the stm32 ECC stuff, I see that some posts already been made on the subject on this forum.

Thanks !

/rygelxvi

[Tesla DeLorean]

Posted on January 13, 2014 at 17:30

MicroSD cards do save a lot of this grief