Nand Flash, FSMC and ECC

[mfranklin]

Posted on July 05, 2012 at 12:03

I'm using and external Samsung NAND Flash chip with an STM32F2 processor.  I have succeeded in writing a driver that can read, write, and erase the chip, but I'm a little confused about how to make use of the FSMC_ECCR2/3 register's value. 

I understand how and when to generate the ECC.  The Samsung NAND Flash has 2048 byte pages, so I have set the ECCPageSize to FSMC_ECCPageSize_2048Bytes.

The Reference Manual does not explain what algorithm is being used to compute the ECC, so how can I implement error correction in addition to error detection?

#ecc #fsmc-nand-ecc-stm32f2

[Tesla DeLorean]

Posted on July 05, 2012 at 13:59

For each 256 byte feed out to the NAND it generates 3-bytes (24-bits) of ECC that you stuff into the appropriate spots in the SPARE area, then your write out the spare area. Thus for 2048 you'll generate 24 bytes. ie process 8 bursts of 512 bytes, yielding 3 bytes each.

On the read back you can compare the values generated against those in the SPARE area, to determine if an error requires fixing. If that fails you pass it off to the error correction routines. You could presumably XOR the generated values against the recorded values to create a syndrome word to predict the location and bit value of the error.

It replaces the software table driven methods of computing the ECC bytes, but is used with the standard software correction routines. ie ones easily found on the internet and published by NAND vendors.

Computing the ECC byte values is trivial in hardware, correction in hardware is difficult. Some of the newer NAND parts can generate these bytes too.

[mfranklin]

Posted on July 06, 2012 at 04:16

Thanks for the prompt and detailed reply.  Much appreciated.

If I need to read the computed ECC value for every 256 bytes read or written, what is the purpose of setting the ECCPageSize property?

[Tesla DeLorean]

Posted on July 06, 2012 at 10:38

As you said the mechanics of the ECC unit are poorly defined/described. I've been using NAND devices on other platforms where the bytes are computed in software. The banks as far as I can tell relate to the high and low order byte channels on 16-bit wide devices. ie push 512 bytes, yielding two 3-byte ECC values.

The algorithm/formula used by the STM32 is capable of detecting 2-bit errors, and *fixing 1-bit errors. You can push this over larger spans if you wish, but it's pretty weak, and would clearly be inadequate if you were using MLC flash parts. Some of the newer/bigger parts can actually assist you in code generation. You should probably review the part specs to see what level of ECC is required for reliable operation and failure detection.

The implementation is mostly left to you, as long as you apply your own method consistently the STM32 and NAND will not be separated and utilized by third party software, ie you define the standard here, how many bytes are included in the computations, where you store the bytes in the spare area, etc.

* The fixing is done in software

[abelloni]

Posted on December 15, 2013 at 16:42

I'm using and external Samsung NAND Flash chip with an STM32F2 processor.  I have succeeded in writing a driver that can read, write, and erase the chip, but I'm a little confused about how to make use of the FSMC_ECCR2/3 register's value. 

I understand how and when to generate the ECC.  The Samsung NAND Flash has 2048 byte pages, so I have set the ECCPageSize to FSMC_ECCPageSize_2048Bytes.

The Reference Manual does not explain what algorithm is being used to compute the ECC, so how can I implement error correction in addition to error detection?

[troy1818]

Posted on January 13, 2014 at 22:34

I am in the same situation as Bellons.

Seems funny to me, that you don't get any information about this.

I did however manage to get an example of how an implementation could look like for:

Device: K9F2G08U0B [TSOP48] 

Manufacturer: Samsung 

Device type: NAND Flash

I have attached the code.

Regards,

/rygelxvi

________________

Attachments :

k9f2g08u0b.7z : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I0tA&d=%2Fa%2F0X0000000biB%2FEBKg8_XRPMeyz6jH85FbK2US5EqZUE6zlWbIQ3LhOgk&asPdf=false

[troy1818]

Posted on January 27, 2014 at 23:37

For those of you that are using MLC NAND and need more ECC power I have attached code that is implementing ECC based on reed-solomon that can help you with this.

The original code (no licence) is written by

****** Mesika. I have made some modifications to make it more stack friendly and

concatenated

all code into 2 files (.c and .h).

The current configuration can correct 5 bit errors for every 128 bytes of data.

RS_TOTAL is the total data and can be up to 255 bytes

RS_ECC is the number of error correcting bytes (can be up to ). Bit errors that can be corrected is then RS_ECC/2.

Hopes this helps someone.

Regards,

rygelxvi

________________

Attachments :

rs_nand.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I12f&d=%2Fa%2F0X0000000biA%2FHBvB5PMIRACgQFOVQdxUMCLW1qCZbA.0NdVXBe.cVyA&asPdf=false

[francescatodiego]

Posted on January 28, 2014 at 08:39

Thanks for sharing

rygelxvi

Working

with a

NAND

flash is not a

trivial job

I started writing

my

own

driver

and

I began to study

the

BCH

algorithm

for

error correction

But I have to

leave everything

to

time constraints

of the project.

STM32F4

include an

SDIO

peripheral

and with the

right 

card

you can use the bus at

maximum

speed

  (

4bit

*

24MHz

)

SD card

solve internally all the

problems related to

NAND flash

But in the future

I hope to

find time to

resume

the study