Multi-Channel I2S Hardware Design on an STM32F413/423

[EDeYo.1]

The microcontroller will be doing little else besides some very light processing on the audio data. The I2S source has a single MCK, SCK, WS, and 4 stereo outputs (3 of which will be used), and the I2S source can ONLY function as a master device, leaving me to use the STM32 as a slave. I see that there is a CKIN pin for I2S labelled as I2S2_CKIN. Looking at the clock routing diagram in the datasheet, it looks like that can be routed to the I2SPLL before being distributed back to I2S peripherals (1,4,5 as well as 2,3). I'll likely provide that as an option in hardware so that I can choose between the external I2S clock input or using the HSI/HSE clock. My question lies in the fact that all of the I2S data channels share WS and SCLK signals. Do I need to buffer/split these signals to go to each peripheral instance, or is there a way that they can be synced between peripherals in firmware? I don't see the mechanism to do it right off the bat in firmware, but looking for someone who may have run into the same issue!

Thanks!

[waclawek.jan]

For slave I2S you probably don't need the I2SxCLK from RCC, or, its particular frequency is not an issue. This follows from the logics of things; nevertheless, ST does not care to convey this detail and when asked, provides a confusing and incomplete answer https://community.st.com/s/question/0D50X00009XkeIy/sai-clock-generator-in-slave-mode (I know it's SAI not I2S, but the issue is the same)

I would try it nevertheless.

You would need to connect the SCK and WS (ie. bitclock and left-right clock) for every I2S module externally (i.e. tie them together and connect to respective output of the I2S source), except for the I2SxExt modules, which have the clocks connected to their respective I2Sx module internally.

I personally would prototype this on a Nucleo board, having I2S sourced from a second Nucleo board (unless the I2S source in question is at hand and readily be connected).

JW

[EDeYo.1]

Regarding tying all the LRCLK/WS together and the BCK/SCK lines together - that's what I envisioned having to do. I wish there was a path between I2S instances for the BCK/LRCLK, but since they're really SPI w/ a dual purpose of I2S, it makes sense that there isn't. I've got an 'F413 development board on the way, and I'll either work on trying to find a proper development PCB for the other half or order another one to act as a master.

Thanks!

[Piranha]

SAI peripherals can be synchronized and you won't need redundant clock lines. Also SAI is much more flexible and has internal FIFO buffers. If possible, I suggest moving to F446, F7, L4 or something other that has 2 SAI peripherals. Just look at it's capabilities:

https://www.st.com/content/ccc/resource/training/technical/product_training/group0/35/bb/c4/23/6a/74/4a/2b/STM32F7_Peripheral_SAI/files/STM32F7_Peripheral_SAI.pdf/jcr:content/translations/en.STM32F7_Peripheral_SAI.pdf

[EDeYo.1]

I've looked at those processors as well, however I need 3 or 4 I2S interfaces - the '413/423 also have 2 SAIs just like the '446 and others you listed.

Thanks,

[Piranha]

https://www.st.com/en/microcontrollers-microprocessors/stm32f413zh.html

It has one SAI peripheral.

Each SAI peripheral has 2 sub-blocks/interfaces. MCUs mentioned by me have two SAI peripherals, which can be synchronized. Therefore you can get up to 4 synchronous I2S streams with those. Look carefully at the SAI presentation link I gave, especially page 6. It's exactly what you need and what it is designed for!

[EDeYo.1]

Thanks for the clarification - I saw the block diagram that looked just like the F413, and missed the fact that it had 2 instances. I'll look into those interfaces more closely.

Thanks!

[Kas]

Came here from the exact SAI question @Community member​ linked:

https://community.st.com/s/question/0D50X00009XkeIySAJ/sai-clock-generator-in-slave-mode

My question is that same one, does the SAI (or I2S) block need a clock source when it is entirely in slave mode?

I will be trying it out without an internal clock source if I can find the time, but does anyone know already? Then I don't have to experiment.

[waclawek.jan]

I did not try myself, but this is a recurring question and I believe we would've heard back from the users if it wouldn't work as expected.

I faintly recall there might've been an attempt from ST to answer this authoritatively, but can't find it.

@Imen DAHMEN​ can please this be answered by ST?

An appnote - one out of dozens - would be appropriate...

JW

[Imen.D]

Hello @Community member​ 

Thank you for bringing these posts to my attention, and sorry for the delayed reply on this as I was on vacation.

• Regarding this post : SAI or SPI clock requirement as I2S slave

I need to know for which product to be more specific. So, I can just give general Inputs:

The kernel clock if needed does not need to be synchronous or frequency accurate like for the master mode. In some devices (generally old IPs) the kernel clock may still be requested. In those cases, there is generally a minimum frequency ratio to respect w.r.t. the serial bitclock.

• For this post SAI Clock Generator in Slave mode, I am waiting an answer from design team.

I'll make sure to post more details here as soon as I hear back from our team.

Hello @EDeYo.1​ ,

If you are using SPI/I2S blocks in slave mode, as far as I know, there is no way to synchronize those IPs internally. The WS provided by the external audio device must be distributed to the WS input of each SPI/I2S block. The same applies for SCK signal.

The STM32F413/423 also embed a SAI, it can help you to save 2 IOs, but with the cost of using a SAI and one SPI/I2S. The SAI contains 2 sub-block, and they can share their WS and SCK.

Note that there is only one SAI, and if you need a third I2S link then an SPI/I2S is needed as well.

Also the SAI can handle multi-channel, if it is supported by your external audio codec, you may save IOs. Handling is maybe a bit more complicated, but it really depends on the application.

Hope my answer helped you!

Thanks

Imen

[Imen.D]

Hi,

Regarding the post SAI Clock Generator in Slave mode, I've heard back from the expert team:

When the SAI is working in slave mode, the SAI clock generator is no longer needed, but the kernel clock (SAI_CK) must still be present.

It is used to perform the clock domain crossing from bits in the APB clock domain to the serial clock domain (such as SAIEN bit).

In slave mode, there is no specific constraint in term of accuracy for the kernel clock, the speed is not critical as well.

The slower the kernel clock is, the more time it will take to transfer bit values in the serial clock domain.

This implementation makes the SAI configuration independent from the serial interface clock, which may not be present.

Hope that I've answered your question :).

All questions or feedback are welcome.

Imen