Multi ADC Mode with STM32F705

[Roman REITER]

Hello. I am using an STM32F7508 board and would like to use 2 ADUs. I ran them without DMA to begin with, which worked. Then I put them into operation with a DMA, where only one of the two worked.

I saw Multi ADC in the data sheet as a deletion for this. But it doesn't work. Also searched forum examples but they didn't work.

Does anyone have an idea what I'm doing wrong?

[christop]

Please refer to example: STM32Cube_FW_F7_V1.17.0\Projects\STM32756G_EVAL\Examples\ADC\ADC_DualModeInterleaved

This example shows how to configure and use ADC1 and ADC2 in multimode with DMA ](in the example it is in dual interleaved mode).

Please also refer to RM0385 v8 section 15.9 Multi ADC mode.

[christop]

From your code you used ADC1 and ADC3. However in dual mode, you should use ADC1 and ADC2 as described in RM0385.

[Roman REITER]

ahhh.. Ok thanks. That means I have to use ADC2 if I use ADC1 and ADC3 => Triplemode?

The number of channels must be the same for all ADCs to operate Multi ADC? That means I can't use 1 channel of ADC2, 2 channels of ADC1 and 6 channels of ADC3?

[christop]

If you use ADC1 and ADC3 in multi mode, then you need to also use ADC2, meaning indeed triple mode.

You can refer to RM0385 ADC_CCR register bitfield MULTI[0:4] for multi ADC mode selection.

It is either all ADCs independent, or dual mode (ADC1 and ADC2 working together and ADC3 independent) or triple mode (ADC1, ADC2 and ADC3 working together).

For the number of channels, I'm still checking.

[Roman REITER]

OK, thanks..

[christop]

Sorry for late reply regarding your remaining question: "The number of channels must be the same for all ADCs to operate Multi ADC? That means I can't use 1 channel of ADC2, 2 channels of ADC1 and 6 channels of ADC3?"

Here is the reply from my colleague who performed some tests to verify based on the 2 below scenarios:

Case #1: all channels with same conversion time:

 Trigger n Trigger n+1
 | |
 | |
ADC1 |--Ch1--|--Ch2--| |--Ch1--|--Ch2--|
ADC2 |--Ch3--| |--Ch3--|
ADC3 |--Ch4--|--Ch5--|--Ch6--|--Ch7--|--Ch8--|--Ch9--| |--Ch4--|--Ch5--|...

Case #2: different conversion time for each channel:

 Trigger n Trigger n+1
 | |
 | |
ADC1 |-------Ch1------|---Ch2---| |-------Ch1------|...
ADC2 |---Ch3---| |---Ch3---|
ADC3 |--Ch4--|--Ch5--|----Ch6----|---Ch7---|-Ch8-|-Ch9-| |--Ch4--|--Ch5--|...

Based on testing, it has been found that only case#1 is feasible in regular simultaneous mode with continuous mode disabled (CONT bit = 0).
In this scenario you have the option to utilize varying numbers of channels for each ADC within the same instance.
However, it's crucial to ensure that all channels within the ADC have the same sampling time since they are sampled simultaneously.
Additionally, the trigger duration should be longer than the longest conversion time to allow the ADC to wait for the longest sequence of conversion to finish before triggering the next sequence.

Otherwise, if you intend to use regular simultaneous mode with continuous mode enabled (CONT bit = 1), in this scenario it is mandatory to use the same number of channels for each ADC and ensure that they have the same sampling time.

Feel free to comment.