More documentation about VOSRDY

[Uwe Bonnes]

Hello,

STM32F4 and F7 have a VOSRDY bit in PWR->CSR. Documentation about the bit is nearly not existant. On a F4, while still running on HSI, I changed the VOS setting. Waiting for VOSRDY in that state never succeeded. Looking for that bit just before switching to PLL however shows that this bit is set.

Some more explanation about that bit is welcome!

[waclawek.jan]

Not all 'F4 are created equal. In 'F40x, VOS is a single bit and can be changed on the fly; in 'F42x or 'F446 VOS is 2 bits and can be changed only if PLL is OFF and the new setting is active when PLL is ON (and has a fixed setting when PLL is OFF).

In the latter case, I believe switching on PLL also changes the effective voltage regulator setting, and when the output voltage reaches a certain level, the VOSRDY gets set; when PLL is switched OFF, VOS switches to its default (lowest) value and VOSRDY is cleared. Whether setting VOSRDY is based on a real comparator, or is simply timed and relies on the given board having installed the prescribed filter capacitors, can be determined by experimentation; I'd bet on the latter.

I agree that documentation can and should be enhanced.

JW

[Mohamed Aymen HZAMI]

Hello,

The VOSRDY is set by hardware after the configuration of the PLL, the correct sequence is as follow :

• Disable the PLL 
• Set voltage scaling configuration 
• Enable the PLL

VOSRDY set to 1

You can refer to product reference manual section 4.4.1 in the VOS description.

Regards,

Mohamed Aymen.

[Uwe Bonnes]

The description

Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit

       0: Not ready

       1: Ready

implies that one could and should check VOSRDY after setting the voltage scaling. However this is doomed for failure. As I now understand VOSRDY, is can only be used if enabling the PLL fails and one wants to look for the reason. The bit description should have at least some remark like: "Only set with PLL enabled".

[David Ashman]

I was experiencing the same issue as @Uwe Bonnes​ where the VOSRDY bit was not being set on my STM32F427IIT6 processor. I finally realized that I first had to enable the PWR module clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); prior to setting the Scale mode. Works well now.

I've verified that the following from the Reference Manual is correct:

"When the PLL is OFF, the voltage scale 3 is automatically selected." and

"After exit from Stop mode, the voltage scale 3 is automatically selected".

However, voltage scale 1 (VOS bits = b11) is preloaded into PWR->CR so if new VOS values are not set at init or post-Stop mode, voltage scale 1 will be active when PLL is enabled.