Missing Cortex-M3 instruction timing

[zzdz2]

Posted on October 11, 2012 at 10:00

ST Cortex-M3 programming manual nicely describes all instruction, how they work and what they do but there is no info how many clock cycles it takes to execute given instruction.

Fortunately I found ARM Cortex-M3 manual and it clearly states all instruction cycles based on a system with zero wait states:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337-

Does anyone know why this info is missing in ST manual?

[Tesla DeLorean]

Posted on October 11, 2012 at 12:32

Does anyone know why this info is missing in ST manual?

Probably because it would be duplicative, and not unique to the ST implementation.

[zzdz2]

Posted on October 11, 2012 at 13:18

At least it should mention instruction timing is available from ARM.

[Tesla DeLorean]

Posted on October 11, 2012 at 17:19

At least it should mention instruction timing is available from ARM.

Kind of think that's the obvious place to start, but I've been doing this too long to be objective.

At least several versions of the reference manuals do refer to ''Related documents'' in the preface that direct you to ARM, some other to ST specific representations

RM0008, Rev 6

Available from www.arm.com:

■ Cortex™-M3 Technical Reference Manual

RM0008, Rev 14

For information on the ARM Cortex™-M3 core, please refer to the STM32F10xxx Cortex™-

M3 programming manual (PM0056).

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00228pdf

RM0090 Rev 1

Available from www.arm.com:

■ Cortex™-M4F Technical Reference Manual, available from:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439c/DDI0439C_cortex_m4_r0p1_trm.pdf

Your far bigger problem however is accurately modeling the surrounding behaviour of things like the write buffers, caches/ART, branch predictions, prefetch, and interactions with AHB and APB at disparate clocks. Instructions like LDM, STM, MUL and DIV will also impact you, the latter being dependent on the data being processed. Static analysis will give you some useful numbers, but I wouldn't rely on them.

A far better strategy would be to benchmark actual code, under realistic conditions, and to use the core cycle counter in the trace unit of most STM32 devices. This would give a much better feel for the internal interactions, and a lot cheaper than having a timing accurate model of the chip.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/DispForm.aspx?ID=20293&RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Run code in SRAM in ASM

[zzdz2]

Posted on October 12, 2012 at 11:23

RM0008, Rev 14

For information on the ARM Cortex™-M3 core, please refer to the STM32F10xxx Cortex™-

M3 programming manual (PM0056).

Yes, actually I meant PM0056, it seems to describe all C-M3 instructions well enough but I couldn't find the timing. At first I though such timing is just unavailable for some reason.

[Tesla DeLorean]

Posted on October 12, 2012 at 12:26

At first I though such timing is just unavailable for some reason.

Yes, and probably because they are mostly single cycle throughput, except when they are not, and complicated by the pipelining, alignment, and factors I've alluded to above.

ARM, and Acorn before them, have always had fantastic documentation, ST far less so.