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RGadd.2
Associate
September 7, 2021
Solved

Minimum pulse width for STM32F2 timer in input capture mode.

I have a low frequency (~1 kHz), low duty cycle signal that I'd like to capture rising edges of. What's the minimum width of those pulses to capture them using a timer in input capture mode?

I see there's a programmable digital filter there, in terms of fDTS and ***_INT, and that the latter is the respective APB bus clock (but divided by no more than 2 from SYSCLK). But what dictates fDTS?

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Tesla DeLorean
Tesla DeLoreanBest answer
Guru
September 7, 2021

TIMCLK = APBCLK *2 or *1 depending on the APB divider

fDTS = TIMCLK / ClockDiv field for the TIM, ie CKD bits in TIMx_CR1

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2 replies

Tesla DeLorean
Tesla DeLoreanBest answer
Guru
September 7, 2021

TIMCLK = APBCLK *2 or *1 depending on the APB divider

fDTS = TIMCLK / ClockDiv field for the TIM, ie CKD bits in TIMx_CR1

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
RGadd.2
RGadd.2Author
Associate
September 7, 2021

Perfect, that's what I was missing. Thanks for the help.