Max portpins -> SRAM sampling speed w/ DMA?

[ecke101]

Posted on October 29, 2009 at 22:56

Max portpins -> SRAM sampling speed w/ DMA?

[ecke101]

Posted on May 17, 2011 at 13:27

Hi,

I'm thinking of trying STM32 for a simple DSO-project. What would be the max speed for reading 12 pins (external parallel ADC) and transfer it to SRAM using DMA? After reading the datasheet I guess somewhere around 10-15Msps?

I also need to latch the output from the ADC in some way I guess before reading from the ADC or what do you think? The ADC will probably be clocked by a clock output from the STM32 or external clock so it's not synced to the reading... Would it be possible to get a clock signal synced to the DMA transfer?

The alternative is using a CPLD and FIFO/SRAM but that's a little too advanced and expensive for my hobby project.

[ This message was edited by: ecke101 on 25-10-2009 23:41 ]

[ This message was edited by: ecke101 on 25-10-2009 23:42 ]

[andy239955_stm1_st]

Posted on May 17, 2011 at 13:27

I presume you are using an external ADC, the internal one is easy to sync.

You should be able to program a timer to do DMA on one edge of the timer output, and use the other edge as the start signal for your external ADC.

You would put the timer in PWM mode, and set the pwm level to ensure that the ADC completes its conversions before the timer rolls over and does DMA.

[ecke101]

Posted on May 17, 2011 at 13:27

Thanks for answering.

Yes it's an external ADC with a max sampling speed of 40Msps. The problem i guess is it wants a clocksignal with 45-55% duty cycle to function properly.

Could I generate such a clocksignal at 8MHz or higher and trigger DMA at every rising or falling edge?

Below that speed there's no point in using an external ADC directly connected to the STM32 I guess. Could as well learn how to use CPLD and save samples to external FIFO/SRAM at 40Msps...