Master Clock STM32H7 SAI Incorrect

[CLeo.1]

Hi everyone,

I am trying to get the SAI1 periperhal configured in I2S Standard mode going on the STM32H753ZI. During my testing sessions I found that my master clock is so far off it doesnt make sense.

Based on the figure 652 within the TRM, it shows that the MCLK_x is produced by having NOMCK = 0 and just having the sai_x_ker_ck divided by MCKDIV,

in which case should have been 98.304MHz/4 = 24.576MHz, but somehow getting 5MHz???

Current Configuration:

• Using SAI1 Block A is Master Rx and Block B is Slave Tx
• SAI1 Block A is Async and Block B is Sync
• Using the frequency of 96kHz
• SAI1 A Clock Kernerl is rated at 98.306MHz
• Using I2S Standard
• Using PLL2_P_CLK to source SAI1 A MCLK
• Over Sampling = 0 (*256)

Things I have done thus far:

• Probbing SAI MCLK getting around 5-6 MHz
• Confirmed that the PLL2_P_CLK is indeed 98.304MHz through MCO2
• Checked wiring
• Double checked pinout

Picture of register of both SAI1 Block A and B

SAI 1 Block A reg:

SAI 1 Block B Reg:

Picture of SAI 1 Block A MCLK

[LCE]

At first glance the register settings look correct.

Have you checked the other clocks? Do you get the 6.144 MHz for SCLK ?

Have you checked the GPIO for MCLK, concerning the correct alternate function ?

As a workaround - mostly because I need other OSR ratios than 256/512 - I use another I2S peripheral as MCLK source.

[CLeo.1]

Looks like I got it working-ish, It seems every other frequency works besides using the sample rate of 96kHz? Is there any particular reason for that?

[CLeo.1]

Even using 96kHz with Over sampling on works. Just not 96kHz with over sampling off

[LCE]

I don't really understand your posts above...

So which clocks are actually how they are supposed to be?

You should have, at fs = 96 kHz:

LRCK = word clock = sampling rate fs = 96 kHz

SCLK = bit clock = 64 * fs = 6.144 MHz

and then your "problem child":

MCLK = (OSR + 1) * fs = 24.576 MHz or 49.152 MHz

Concerning the GPIO, have you checked the alternate function, and the speed setting?

Or maybe another peripheral sets up that GPIO after SAI init and takes over?

[CLeo.1]

Sorry about the confusion,

The clock I am using for the SAI kernel is PLL2_P_CLK. Its set at 98.304MHz and its working correctly.

What I was trying to say was I have tried another sampling frequency of 48kHz, and 192kHz and they all output the correct clocks (FS, MCLK, and SCLK) its just whenever I have the sample frequency as 96kHz things go wonky. When I say sampling frequencyof (x)kHz I meant changing the MCKDIV and using the diagram above to get FS as the desired sample frequency. So the reply above me is what I am not getting however if I use another other frequencies I get the correct clocks.

Theres no other periperhal enabled as SAI is the only thing enable within my system right now

Concerns for the GPIO is that everything is set correctly all GPIO are set to max speed and the alt function are correct, as mentioned changing the FS to 48 or 192kHz works, I have audio being outputted right now, its just for 96kHz not working

[LCE]

@CLeo.1​  Have you solved that problem? If yes, how?

If not: what are the exact register settings at 96 kHz, the peripheral clock, what do the output clocks do ?