Manage STM32F205RG flash programming and other tasks at the same time.

[Smit]

Hi,

I have an application where the device must respond to another device as a part of UART communication @ 1 sec. However, at the same time to log 200 bytes of data upon update of a variable, I need to log it into Flash at Sector 11 of STM32F205RGYX_FLASH MCU so reprogramming Flash takes 1-2 sec of blocking erase cycle as stated in the datasheet, and then by it missed to respond to messages from another device also observed timeout at another end.
​Can we have any mechanism that reduces the erase cycle time for Sector 11 or any optimized way out to manage communication and reprogramming flash simultaneously?

Thanks,

[Peter BENSCH]

Welcome, @Community member​, to the community!

Well, what you are observing is a typical case of single bank flash limitation. In order to run a program and have data in the flash at the same time, you need either so-called dual bank flash or a routine that you execute from RAM.

Dual bank flash requires additional effort (separation of the flash into two blocks, second charge pump, etc), so it is not offered in the STM32F0 family for cost reasons. So you should either switch to a family and derivative that support dual bank flash (e.g. STM32L0, STM32G0), or copy your routine needed while writing the flash to RAM and execute it there.

Hope that helps?

Regards

/Peter

[Danish1]

I'm not sure which stm32f0 you mean. Please could you give us more of the part number.

I had a quick check on a couple of them and they show mass erase times of 40 ms.

FLASH programming or erase times are a significant problem. The stm32 processor cannot read from FLASH at the same time as either erasing or writing it.

• Some (larger) stm32 have "dual-bank" FLASH, where one can perform a read or write to one bank while executing code from the other.
• If you have small urgent functions that must keep running during FLASH programming / erase, you can put them in RAM and execute from there. But you must ensure that all accesses are to/from RAM during this time - for example any interrupts and the vector table will also have to be in RAM.
• Why must the 128k page be erased? Could you reorganise the memory so that smaller pages get erased instead? (Note: If this is for firmware update, most people accept that there is some loss of functionality during the update process).

[Smit]

Pardon mentioning part number here as STM32F205RGYX.

[Peter BENSCH]

The same applies to STM32F2, except that other families can be considered as alternatives, e.g. STM32F4 or STM32H5.