LSE READY PROBLEM FOR RTC

[irmakci]

Posted on December 13, 2013 at 23:33

Hello everybody,

i use stm32f100c8 mcu for our design and i have problem with LSE ready problem. 

i used stm32 rtc calendar example from STM32F10x_StdPeriph_Lib_V3.5.0 . For this example, i have this problem. i looked errata and i saw ''LSE start-up in harsh environments'' section. and i connected 20M ohm resistor parallel to my osc. . Although i connected this resistor, i have still same problem with LSE ready on line

/* Enable LSE */

  RCC_LSEConfig(RCC_LSE_ON);

  /* Wait till LSE is ready */

  while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)

  {}

In this example

1. why they do not make enable BKP and PWR clocks for accessing backup registers when they try to read first time as follows. Becuase ref manual says that we must enable clocks before accesing backup registers???

if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)

{

}

2. Even if i changed this part , i still have problem for LSE ready problem. 

3. And for our other design, interestingly it works sometimes, and sometimes this part does not work. What is the MAIN problem for this? 

What do you suggest for this problem?

 

Best Regards

#rtc-lse-crystal-ready-weird

[irmakci]

Posted on December 13, 2013 at 23:35

my problem is that i wait on this while loop forever!!!

Best Regards

[Tesla DeLorean]

Posted on December 14, 2013 at 00:35

What is the part# and characteristics of the crystal you are attempting to use?

The load capacitance should be 6-7pF, so not a 9pF or 12pF crystal.

MC306-G-06Q-32.768

http://search.alkon.net/cgi-bin/pdf.pl?pdfname=07353.pdf

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/APPLICATION_NOTE/CD00221665.pdf

[irmakci]

Posted on December 14, 2013 at 21:30

Thank you for answer Clive. i will check this problem on monday week and i will publish results here. But i wonder why calendar example works normally (except my design ) because it does not make enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register when it accesses as follows first time. 

  /* NVIC configuration */

  NVIC_Configuration();

  if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)

  {

    /* Backup data register value is not correct or not yet programmed (when

       the first time the program is executed) */

    printf(''\r\n\n RTC not yet configured....'');

    /* RTC Configuration */

    RTC_Configuration();

    printf(''\r\n RTC configured....'');

    /* Adjust time by values entered by the user on the hyperterminal */

    Time_Adjust();

    BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);

  }

it means that when we read backup registers, we do not need to enable clocks related? But reference manual says that we must enable when we want to access backup registers!

Best Regards.

[Tesla DeLorean]

Posted on December 15, 2013 at 15:47

Enabling the clocks for PWR/BKP and enabling access first would be advisable.

If the LSE starts unreliably, or slowly, it's most likely an issue with the characteristics of the external circuit.

[irmakci]

Posted on December 18, 2013 at 15:55

hi clive 

thank you for answer. you are right. we learnt that our hardware engineer used 12.5 pf because of old stm8 designs. now we changed our OSC. section for 6pf. And we checked some card with 12.5pf and 6pf . for both osc, it works. but datasheet says that we must use 6 or 7 pf for osc. section. Thank you 

Best Regards...