Low Power Run mode (LPR) frequency and power consumption
I have a few questions about how the LPR works.
First off, the RM says "Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz."
1. What is meant by system clock here? SYSCLK or core clock (HCLK)? As far as I can see from clock tree, you can't have SYSCLK < 4 MHz if your clock source is external crystal (HSE), so if SYSCLK is meant here, the LPRun mode is achievable only when clocking from HSI16 with /8+ prescaler.
2. What would be with LPR if I exceed 2 MHz? As far as I understand, the MCU has no straight way to determine the actual clock frequency. So now even if my HCLK exceeds 2 MHz, I can successfully activate LPR in the register (and even the power consumption lowers by 10-20% which is nice, but this isn't that much the datasheet claims for actual LPR). What are the consequences? (Unstable work? The mode is actually not activated?)
(STM32G0B1)
